Host Non-Volatile Memory Binding for Storage I/O Latency
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Solution Overview
Problem
The high latency associated with PCIe interfaces in storage systems, particularly evident when handling many small random I/O operations, hinders performance in storage systems that use non-volatile memory, as existing low-latency software-based caches compromise write operation durability by requiring synchronous data flushing.
Innovation Solution
The binding of host non-volatile memory to storage devices creates a unified non-volatile memory space, bypassing PCIe latency by using a designated portion of the host non-volatile memory as a write-back cache, accessible via a local memory fabric, with binding information stored in partition tables and configuration registers during the boot process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCIe interfaces are used to connect host processor and storage devices, then high bandwidth interconnection is achieved, but high latency occurs particularly for small random I/O operations
Solution Approach 1:
The patent introduces host non-volatile memory as an intermediary component between the storage device and PCIe interface. This bound non-volatile memory portion serves as a buffer that captures write operations locally, eliminating the need for high-latency PCIe transactions for each I/O operation while maintaining data durability through write-back caching mechanisms.
2Loss of time
If volatile memory is used as software-based cache to reduce latency, then I/O latency is reduced, but write operation durability is compromised due to synchronous flushing requirements
Solution Approach 1:
The patent changes the fundamental parameter of cache memory from volatile to non-volatile. This parameter change enables the cache to maintain data durability characteristics while providing low-latency access, as non-volatile memory inherently preserves data without requiring synchronous flushing to storage devices.
Solution Approach 2:
The patent replaces expensive volatile memory-based software caches with a more durable non-volatile memory solution that eliminates the need for complex cache management software and synchronous flushing protocols, providing both cost and performance benefits.
3Loss of time
If bound host non-volatile memory is used as write-back cache, then write completion latency is dramatically reduced, but system complexity increases due to binding configuration requirements
Solution Approach 1:
The patent performs the binding configuration action during system boot or initialization before normal operation begins. The BIOS or firmware pre-configures the binding between host non-volatile memory and storage devices by storing binding information in partition tables, eliminating the need for complex runtime configuration and simplifying the user experience.
Data Source
AI summary
A storage system in one embodiment comprises a host processor that includes a first non-volatile memory. The storage system further comprises a storage device that is coupled to the host processor. A designated portion of the first non-volatile memory is bound to the storage device responsive to storage of binding information in at least one partition table associated with the first non-volatile memory. The storage device may include a storage controller that includes a configuration register space. The binding information may be copied from the one or more partition tables to the configuration register space in conjunction with a boot operation of the host processor. The host processor illustratively comprises a storage device driver having access to the binding information copied to the configuration register space of the storage device. The storage device driver may be configured to utilize the designated portion of the first non-volatile memory that is bound to the storage device as a write back cache.