Host Performance Acceleration Mode for eMMC Read Latency
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Solution Overview
Problem
The increasing capacity of embedded multi-media card (eMMC) storage devices leads to a significant burden on conventional management methods due to the large size of logical-to-physical mapping (L2P) tables, resulting in excessive time spent on L2P translation, which hampers the performance of data reads.
Innovation Solution
The implementation of a Host Performance Acceleration (HPA) mode that allocates system memory as an HPA buffer to store L2P mapping entries, allowing the host side to issue read commands with physical addresses directly to the flash controller, thereby reducing the need for extensive L2P translation by the flash controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device capacity is increased to store more data, then the storage capacity is improved, but the size of logical-to-physical mapping (L2P) table increases, resulting in excessive translation time
Solution Approach 1:
The patent extracts the L2P translation function from the flash controller to the host side. The host maintains a cache of L2P mapping entries and performs translation operations independently, removing the translation burden from the flash controller and reducing translation time for data read operations.
Solution Approach 2:
The patent implements preliminary action by having the host pre-fetch and cache L2P mapping entries before they are needed for data translation. The host proactively loads mapping tables into its memory, so that when data read operations occur, the translation can be performed immediately using the cached entries without waiting for flash controller translation.
2Quantity of substance
If the L2P table size increases to support larger device capacity, then the storage capacity is improved, but the device complexity increases due to the burden of managing large L2P tables
Solution Approach 1:
The patent extracts the L2P table management responsibility from the flash controller to the host side. The host is responsible for maintaining, caching, and managing the L2P mapping entries, while the flash controller only needs to provide the mapping data initially and then handle simple address translation based on host-provided physical addresses.
Solution Approach 2:
The host acts as an intermediary between the host file system and the flash controller. It maintains the L2P mapping cache and handles the complexity of mapping management, translating logical addresses to physical addresses using its cached data, and then issuing simplified commands to the flash controller with the translated physical addresses.
3Ease of operation
If the flash controller performs all L2P translation operations, then the data access path is simplified, but the read performance deteriorates due to the time spent on translation
Solution Approach 1:
The patent extracts the time-consuming L2P translation operation from the flash controller's data path. The host performs translation using its cached L2P entries and provides the flash controller with physical addresses directly, allowing the flash controller to focus on fast data retrieval without translation overhead.
Solution Approach 2:
The host performs preliminary L2P translation using its cached mapping entries before issuing read commands to the flash controller. This preliminary action eliminates the need for the flash controller to perform translation during the actual data read operation, significantly improving read performance.
Data Source
AI summary
The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.