Host Queue Address Translation Without ATC Cache Overhead
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Solution Overview
Problem
The use of address translation cache (ATC) for host queue pointers in SSDs is expensive in terms of RAM usage, area, cost, and power consumption, and increases complexity and overhead.
Innovation Solution
Bypass the ATC by directly using translated addresses for host queue pointers, utilizing the controller to perform address translation and manage queues without ATC, employing create queue and invalidate operations to maintain translated addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address translation cache (ATC) is used to translate addresses for host queues, then address translation functionality is provided, but RAM usage, area, cost, and power consumption increase significantly
Solution Approach 1:
The patent extracts the address translation functionality from the ATC hardware structure and relocates it to software implementation in the host processor. The host processor maintains translation tables and performs address translation operations through software routines, eliminating the need for dedicated ATC RAM in the storage device.
Solution Approach 2:
The host processor is utilized to perform multiple functions including address translation, queue management, and data processing. By making the host processor universal and capable of handling address translation tasks, the patent eliminates the need for specialized ATC hardware in the storage device.
2Reliability
If address translation cache (ATC) is used to translate addresses for host queues, then address translation is performed, but device area and cost increase
Solution Approach 1:
The ATC component is extracted from the storage device architecture and its functionality is moved to the host processor. This removal reduces the physical area requirements of the storage device while maintaining address translation capability through software-based implementation.
3Reliability
If address translation cache (ATC) is used to translate addresses for host queues, then address translation service is provided, but power consumption increases
Solution Approach 1:
The power-consuming ATC hardware is extracted from the storage device and its functionality is transferred to the host processor. Although the host processor will consume power for address translation operations, the overall system power consumption is optimized by eliminating dedicated ATC hardware in the storage device.
4Speed
If address translation cache (ATC) is used for host queue pointers, then translation is cached for quick access, but complexity and overhead increase
Solution Approach 1:
The complex ATC hardware structure is extracted and replaced with software-based address translation in the host processor. While software translation may appear slower, the elimination of hardware complexity and the ability to use virtual memory management unit (MMU) capabilities maintain acceptable translation speeds while dramatically reducing system complexity.
Data Source
AI summary
Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.