Host-Resident Error Correction for Resource-Limited Memory
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Solution Overview
Problem
Existing memory devices face limitations in performing error correction due to inadequate processing resources, leading to increased time and processing demands, which can result in inaccurate data correction and system failures, especially as data storage capacity and process variability increase.
Innovation Solution
Shift the error correction operations from the memory device to a host computing system, utilizing specialized circuitry for error correction, allowing for more powerful processing resources to handle error correction tasks, thereby reducing the burden on memory devices and improving data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction operations are performed on the memory device, then data errors can be corrected, but processing resources are insufficient leading to increased correction time and potential system failures
Solution Approach 1:
The patent extracts the error correction function from the memory device and relocates it to the host computing system. The memory device no longer performs error correction operations, instead transferring raw data to the host which has dedicated error correction logic. This extraction resolves the contradiction by removing the processing burden from the memory device while maintaining correction capabilities on the host with sufficient resources.
Solution Approach 2:
The patent introduces an intermediary error correction logic layer on the host computing system that sits between the memory device and the application processing. This intermediary handles all error correction operations, receiving data from the memory device and providing corrected data to applications. This mediator approach allows the memory device to focus on storage while the host handles correction, resolving the resource insufficiency issue.
2Reliability
If processing resources on memory devices are increased to improve error correction capability, then more errors can be corrected, but device complexity and cost increase
Solution Approach 1:
The patent extracts the complex error correction processing logic from the memory device and places it entirely on the host computing system. This eliminates the need for sophisticated error correction circuits within the memory device itself, maintaining simple memory device architecture while achieving robust error correction through the host's processing capabilities.
Solution Approach 2:
The patent leverages the host computing system's universal processing capabilities to handle error correction. Instead of dedicating specialized error correction hardware to each memory device, the host's general-purpose processor and error correction logic serve multiple memory devices, reducing overall system complexity while maintaining correction effectiveness.
3Reliability
If error correction is performed on the memory device, then data integrity is maintained, but data throughput is reduced due to processing time
Solution Approach 1:
The patent implements preliminary error correction processing on the host computing system, where error correction logic is pre-configured and ready to process data as soon as it arrives from the memory device. This preliminary preparation of correction algorithms and resources on the host eliminates processing delays that would occur if correction were performed on the memory device during data transfer, thereby maintaining both integrity and throughput.
Data Source
AI summary
Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.