Host-Resident FTL Address Validation
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Solution Overview
Problem
Flash memory systems face performance degradation due to constrained cache sizes in mobile storage devices, leading to random read performance issues and potential incorrect access of flash memory addresses without valid verification.
Innovation Solution
Implementing a host-resident Flash Translation Layer (FTL) that uses host memory as a cache for FTL mapping tables, validating physical addresses through decryption and verification to ensure accurate access and prevent malicious access, while maintaining coherency and updating the mapping table during idle host operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If host memory is used as cache for FTL mapping tables, then random read performance is improved, but system complexity increases due to additional validation requirements
Solution Approach 1:
The patent introduces an encryption/decryption module as an intermediary between the host memory cache and the flash memory access. This module validates physical addresses by decrypting them against encrypted flash translation tables, ensuring data integrity while enabling fast random read access through host-resident caching. The intermediary resolves the contradiction by adding validation capability without requiring complex changes to the underlying storage architecture.
Solution Approach 2:
The patent applies preliminary action by pre-encrypting physical addresses and storing encrypted flash translation tables in host memory before actual data access operations. This advance preparation allows for rapid validation during random read operations, improving performance while the one-time encryption setup cost is amortized over subsequent accesses.
2Reliability
If physical addresses are decrypted and validated, then data access accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies asymmetry by implementing unidirectional encryption of physical addresses using a secret key that exists only in the memory device. The decryption operation is performed selectively only when validation is needed, while normal cached accesses proceed without full decryption overhead. This asymmetric approach ensures data access accuracy through validation while minimizing processing time for routine operations.
3Reliability
If mapping table coherency is maintained during host operations, then data integrity is improved, but operational flexibility is reduced
Solution Approach 1:
The patent implements feedback mechanisms where the memory device monitors host memory access patterns and validates physical addresses against encrypted flash translation tables. When coherency issues are detected, the system automatically refreshes or updates the mapping tables in host memory, ensuring data integrity while allowing flexible host operations to continue. The feedback loop maintains reliability without imposing rigid constraints on host operational flexibility.
Data Source
AI summary
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.