Host-Side Address Translation for Multi-Plane NAND Flash Memory
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Solution Overview
Problem
Existing storage systems face challenges in efficiently utilizing multi-plane and multi-die memory architectures due to limitations in addressing and timing restrictions, leading to inefficiencies in data access and storage, particularly with NAND flash memory, where data cannot be written to previously used locations until erase units are erased, causing latency and bus idle time.
Innovation Solution
A memory controller that maintains information on memory geometry and multi-plane capabilities, allowing hosts to directly manage physical address allocation and organization, enabling efficient multi-plane access by translating logical addresses to physical addresses and optimizing IO operations, thereby reducing memory controller address translation requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-plane access is implemented with common IO and address circuitry, then data access parallelism is improved, but addressing and timing restrictions limit the effectiveness of multi-plane operations
Solution Approach 1:
The patent segments the address space into multiple independent plane address spaces, each with its own address mapping. This allows the host to directly address specific planes without being constrained by common address circuitry restrictions, enabling true multi-plane parallel access while maintaining addressing flexibility for each plane independently.
Solution Approach 2:
The patent introduces a new dimension of address translation by implementing a host-side translation layer that maps logical addresses to physical addresses across multiple planes. This additional translation dimension allows the system to overcome the limitations of common IO circuitry by providing independent addressing paths to each plane, thereby improving both parallelism and addressing versatility.
2Quantity of substance
If NAND flash memory is used with conventional memory controller management, then data storage capacity is achieved, but programming and erasing latencies in the hundreds of microseconds constrain system performance
Solution Approach 1:
The patent implements preliminary action by allowing the host to pre-stage write operations in memory buffers before actual programming occurs. The host can organize and prepare data for multiple planes in advance, and the memory controller can pre-coordinate erase operations across planes, thereby reducing the impact of programming and erasing latencies on overall system performance.
Solution Approach 2:
The patent enables continuity of useful action by implementing overlapping operations where the host can issue read commands to one plane while write or erase operations are正在进行 on other planes. The multi-plane architecture with independent addressing allows these operations to proceed simultaneously without idle time, maintaining continuous productive use of the memory subsystem.
3Ease of operation
If memory controller performs logical-to-physical address translation for multi-plane memory, then data access is simplified, but channel bandwidth improvement is offset by additional translation latency
Solution Approach 1:
The patent extracts the address translation function from the memory controller and implements it at the host side. By moving the translation layer to the host, the system eliminates the translation latency bottleneck in the memory controller path. The host can perform translations using its own processing resources without adding latency to the memory access path, while still providing simplified access through the abstraction layer.
Solution Approach 2:
The patent introduces an intermediary address translation layer at the host that mediates between logical addresses and physical plane addresses. This intermediary translation mechanism allows the host to manage multi-plane access efficiently without requiring the memory controller to perform time-consuming translations, thereby reducing translation latency while maintaining ease of operation through the logical address abstraction.
4Quantity of substance
If data is written to NAND flash memory locations, then data storage is achieved, but data cannot be written to previously-used locations until erase units are erased, causing bus idle time
Solution Approach 1:
The patent implements preliminary action by enabling the host to pre-coordinate erase operations across multiple planes before initiating write operations. The host can identify erase units that will be needed for future writes and proactively erase them in the background, so that when write operations are needed, the target locations are already ready. This eliminates bus idle time and improves overall productivity while maintaining full data storage capability.
Data Source
AI summary
This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.