Host-Side Tier Cache Coherency for 3D Xpoint in Distributed File Systems

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Solution Overview

Problem

Clustered/distributed file systems face challenges in maintaining cache coherency when using non-volatile memory technologies like 3D Xpoint, as these do not participate in the existing cache coherency protocols, leading to potential data inconsistencies and increased costs due to the reliance on volatile RAM.

Innovation Solution

Implementing a host-side tier cache coherency management system that coordinates synchronization of writes and invalidations independently from the file system buffer cache, using a 'snoop' type write-back cache coherency model to ensure cache coherency across nodes, including the use of non-volatile memory technologies like 3D Xpoint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If persistent cache (3D Xpoint) is used below VRAM file buffer cache, then cost is reduced and non-volatility is achieved, but cache coherency cannot be maintained because persistent cache does not participate in C/DFS cache coherency protocol

Engineering Contradiction:
Improvecache coherencyVSAvoidcache hierarchy complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a persistent cache coherency management component that acts as an intermediary between the persistent cache and the C/DFS cache coherency protocol. This intermediary translates and forwards cache invalidation messages from peer nodes to the persistent cache, enabling the persistent cache to participate in the coherency protocol without requiring fundamental changes to the existing C/DFS architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the cache coherency management into two independent layers: file system buffer cache coherency (managed by C/DFS) and host-side persistent cache coherency (managed by the new component). This segmentation allows each layer to be optimized independently while maintaining overall system coherency through coordinated invalidation messaging.

Inventive Principle:
Principle #1Segmentation

2Speed

If VRAM is used for cache, then fast read/write access is achieved, but cost increases and data loss vulnerability occurs

Engineering Contradiction:
Improveread/write access timeVSAvoiddata loss vulnerability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies local quality by assigning different memory technologies to different caching needs: VRAM is used for the file buffer cache where speed is critical and data loss is acceptable (since it gets flushed to persistent storage), while persistent cache (3D Xpoint) is used for the host-side cache where both speed and data persistence are important. Each cache layer has optimized characteristics for its specific function.

Inventive Principle:
Principle #3Local quality

3Device complexity

If persistent cache is used, then cost is reduced compared to VRAM, but cache coherency protocol participation fails

Engineering Contradiction:
Improvecache costVSAvoidcache coherency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent makes the persistent cache coherency management component a universal solution that works with existing C/DFS architectures while enabling persistent cache participation. It provides multi-functionality by handling both the translation of cache invalidation messages and the coordination with peer nodes, making the persistent cache interoperable with the existing file system cache coherency infrastructure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Productivity

If write operations are held in persistent cache, then performance is improved, but data consistency appears incorrect to peer nodes

Engineering Contradiction:
Improvewrite performanceVSAvoiddata consistency visibility
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent implements feedback mechanisms where the persistent cache coherency management component receives cache invalidation messages from peer nodes and forwards them to the persistent cache. This feedback loop ensures that when peer nodes detect changes in file system objects, the persistent cache is notified and can invalidate or update its copies, maintaining data consistency across the distributed system.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11210263B1Using persistent memory technology as a host-side storage tier for clustered/distributed file systems, managed by cluster file system
Publication Date: 2021.12.28 EMC IP HLDG CO LLC
  • US11210263B1 patent drawing
  • US11210263B1 patent drawing
  • US11210263B1 patent drawing

AI summary

Embodiments are described for a multi-node file system, such as a clustered or distributed file system, with a file system buffer cache and an additional host-side tier non-volatile storage cache such as 3DXP storage. Cache coherency can be maintained by one of three models: (i) host-side tier management, (ii) file system management, or (iii) storage array management. performing a storage tier-specific file system action in a file system that comprises a namespace that spans multiple tiers of storage.