Direct Memory Access Between Host and Smart NIC

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Solution Overview

Problem

Existing communication methods between hosts and internal smart network interface controllers (SNICs) in data centers are indirect, leading to slower data transmission and inefficient use of bus connections.

Innovation Solution

Implementing direct memory access (DMA) processes between the memory of a host and the memory of a smart network interface controller (SNIC) connected to the host's bus, using threads running on both the host and the SNIC to facilitate direct data access over the bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If indirect packet-based communication is used between host and NIC, then data can be transmitted between systems with different operating systems, but transmission speed is slowed down

Engineering Contradiction:
Improvecompatibility between host and NIC operating systemsVSAvoiddata transmission speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces a communication channel that acts as an intermediary between the host and NIC, allowing direct memory access while maintaining compatibility between different operating systems. The channel includes a host interface and NIC interface that coordinate data transfer without requiring full packet processing through both operating systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The communication channel is segmented into distinct components: a host interface portion, a NIC interface portion, and direct memory access pathways. This segmentation allows each component to operate independently at optimal speeds while maintaining overall system compatibility.

Inventive Principle:
Principle #1Segmentation

2Speed

If direct memory access channel is established between host and NIC, then data transmission speed is improved, but system complexity increases

Engineering Contradiction:
Improvedata transmission speedVSAvoidcommunication channel structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the communication channel functionality directly into the memory interface structure, combining host interface, NIC interface, and memory access pathways into an integrated system. This reduces overall complexity by eliminating separate packet processing components while maintaining direct memory access capabilities.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If full packet processing is performed through NIC operating system, then data can be properly formatted and transmitted, but transmission efficiency is reduced

Engineering Contradiction:
Improvedata packet formatting accuracyVSAvoiddata transmission efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the essential data formatting and transmission functions from the full packet processing pathway. The communication channel provides direct memory access for data transfer while only performing necessary formatting operations, eliminating redundant packet processing steps that reduce efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Data is prepared and formatted in advance in the host memory before being transferred through the communication channel. This preliminary action allows the actual data transfer to proceed at maximum speed without requiring extensive processing during the transmission phase.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12292845B2Methods and systems for establishing direct communications between a server computer and a smart network interface controller
Publication Date: 2025.05.06 VMWARE INC
  • US12292845B2 patent drawing
  • US12292845B2 patent drawing
  • US12292845B2 patent drawing

AI summary

This disclosure describes processes for performing direct memory access (“DMA”) between memory of a host and memory of a smart network interface controller (“SNIC”) connected to a bus of the host. The host runs a host thread in a processor of the host and the SNIC runs a SNIC thread in a processor of the SNIC. The host thread and the SNIC thread facilitate direct access of the SNIC thread to memory locations in the memory of the host. The SNIC thread can fetch data directly from and/or write data directly to the memory locations of the memory of the host over the bus.