Host Storage Address Mapping for Random Data
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Solution Overview
Problem
Storage systems face performance issues and increased write amplification due to handling random data, as they are optimized for sequential data, leading to inefficiencies in logical-to-physical address mapping and garbage collection.
Innovation Solution
A host processor maps random data to imaginary logical addresses extending beyond the memory's logical capacity, allowing sequential storage and reducing the need for frequent logical-to-physical address translations, while the storage system designates separate blocks for temporary data storage and foregoes garbage collection on these blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If storage systems handle random data using traditional logical-to-physical address mapping, then data can be stored, but write amplification increases and performance deteriorates
Solution Approach 1:
The patent introduces an intermediary layer (the extended logical address space and mapping mechanism) between the host and physical storage blocks. Random data from multiple applications is mapped to sequential imaginary logical addresses, which then map to physical blocks, reducing direct random access to the physical storage medium and thereby reducing write amplification
Solution Approach 2:
The patent segments the storage system into distinct regions: real logical addresses for permanent data and extended imaginary logical addresses for temporary random data. This segmentation allows the system to handle random and sequential data differently, optimizing performance for each type
2Productivity
If storage systems are optimized for sequential data, then sequential write performance is good, but random data handling becomes inefficient
Solution Approach 1:
The patent inverts the traditional approach by mapping random data to sequential imaginary logical addresses instead of mapping sequential data to sequential physical addresses. This inversion allows random data to be handled efficiently by leveraging the sequential access optimization of the storage system
3Ease of operation
If frequent logical-to-physical address translations are performed, then random data can be accessed, but access time increases
Solution Approach 1:
The patent performs preliminary mapping of random data to sequential imaginary logical addresses before actual storage operations. This preliminary action organizes the data in a sequential pattern that reduces the need for frequent and complex logical-to-physical address translations during subsequent access operations
4Reliability
If garbage collection is performed on all blocks, then storage reliability is maintained, but system performance decreases
Solution Approach 1:
The patent applies different quality policies to different regions: garbage collection is applied to real logical address blocks to maintain reliability for permanent data, while it is foregone for extended imaginary logical address blocks that contain temporary random data. This local differentiation maintains reliability where needed while preserving performance
Data Source
AI summary
A storage system, host, and method for extended and imaginary logical-to-physical address mapping are provided. In one embodiment, a host maps logical block addresses of a plurality of random data to a sequential set of imaginary logical addresses that extend beyond a logical capacity of a memory in a storage system. The host sends a request to the storage system to write the plurality of random data in the sequential set of imaginary logical addresses. Other embodiments are provided.