Host Storage Mapping Table Architecture for Read Latency
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Solution Overview
Problem
The limited SRAM resources in storage chips lead to inefficient mapping table searches, resulting in low hit ratios and increased response times for read requests, as full mapping tables cannot be stored, requiring multi-level searches and entry flushing, which severely affect response speed.
Innovation Solution
Storing the mapping relationship between logical and physical addresses in both the host chip and storage chip, allowing for efficient retrieval and updating of mapping relationships using an extended domain in the UFS protocol, enabling the host chip to send read and write requests with more physical address information and the storage chip to update mapping relationships in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SRAM resources are limited in storage chips, then device complexity is reduced, but mapping table search efficiency deteriorates due to low hit ratio and increased response time
Solution Approach 1:
The patent introduces a new dimension to address the SRAM limitation by implementing a two-layer mapping structure: a first mapping table in SRAM for frequently accessed mappings and a second mapping table in flash memory for less frequently accessed mappings. This dimensional expansion allows the system to maintain fast access for common operations while storing comprehensive mapping data, thereby improving read request response speed without requiring the SRAM to hold the entire mapping table.
Solution Approach 2:
The mapping table is segmented into two separate storage locations based on access frequency and capacity requirements. The first mapping table in SRAM stores frequently accessed logical-to-physical address mappings, while the second mapping table in flash memory stores the complete mapping data. This segmentation allows the SRAM to remain small and fast for critical operations, while the flash memory provides comprehensive storage capacity, resolving the contradiction between limited SRAM resources and comprehensive mapping table storage.
2Reliability
If multi-level search is performed to find mapping tables, then mapping completeness is improved, but response time increases severely
Solution Approach 1:
The system performs preliminary action by pre-loading frequently accessed mapping entries into the first SRAM mapping table before they are needed. This allows the most common read requests to be satisfied directly from the fast SRAM memory without triggering multi-level searches. The preliminary loading of critical mapping data eliminates time-consuming search operations for frequently accessed entries, significantly reducing read request response time while maintaining complete mapping functionality through the second flash memory table.
3Quantity of substance
If entry flushing is performed when SRAM has insufficient space, then mapping table capacity is maintained, but operational efficiency deteriorates due to additional overhead
Solution Approach 1:
The patent implements a copying mechanism where mapping entries are copied from the second flash memory table to the first SRAM table based on access patterns and space availability. This selective copying allows the system to maintain a compact but sufficient mapping table in SRAM for active operations, while the complete mapping data remains in flash memory. The copying operation occurs only when necessary, avoiding continuous flushing overhead while ensuring the SRAM table has adequate capacity for current operational needs.
Data Source
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AI summary
This application provides an information processing method, an apparatus, a device, and a system. The information processing method includes: A host chip determines first information, where the first information includes a first logical address set. The host chip generates first indication information, where the first indication information includes the first logical address set and a first physical address set that is determined based on a mapping relationship between a logical address and a physical address and that corresponds to the first logical address set, the first physical address set includes N physical addresses, the N physical addresses are in a one-to-one correspondence with N logical addresses included in the first logical address set, and N is an integer greater than or equal to 2. The host chip sends a first request to a storage chip connected to the host chip, where the first request includes the first indication information. Correspondingly, this application further provides a corresponding apparatus, device, and system. In this application, a response speed of a read request can be effectively increased.