Host Sync Proxy Module for Tile Barrier Synchronization
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Solution Overview
Problem
In multi-threaded processor systems, especially those using bulk synchronous parallel (BSP) communication schemes, synchronizing with a host processor incurs a significant latency penalty, which can slow down overall throughput and increase interrupt latency, as each tile must frequently interact with the host for synchronization, leading to reduced performance in machine intelligence applications.
Innovation Solution
A hardware mechanism is introduced that allows a sub-processor to allocate sync credits, enabling it to progress through multiple synchronization barriers without direct host involvement, using a host sync proxy module to manage credits and reduce the need for frequent host interactions, thereby minimizing latency penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent barrier synchronizations are performed with the host processor, then synchronization accuracy is improved, but latency increases and throughput decreases
Solution Approach 1:
The host processor pre-allocates a pool of synchronization barriers and assigns them to sub-processor tiles before the tiles begin computation. This preliminary allocation allows tiles to independently select and use barriers from the pool without needing to request or wait for host involvement at each synchronization point, thereby reducing latency while maintaining synchronization accuracy through the pre-established barrier infrastructure.
2Reliability
If frequent barrier synchronizations are performed with the host processor, then synchronization accuracy is improved, but productivity decreases
Solution Approach 1:
The synchronization barrier resource is segmented into a pool of individual barriers that can be independently allocated and used by different tiles. This segmentation allows multiple tiles to perform synchronizations concurrently using different barriers from the pool, eliminating the bottleneck of sequential host involvement and thereby improving throughput while maintaining synchronization accuracy through the structured barrier pool management.
3Ease of operation
If direct host involvement is required for each barrier synchronization, then synchronization control is improved, but device complexity increases
Solution Approach 1:
A barrier pool management mechanism is introduced as an intermediary layer between the host processor and the sub-processor tiles. The host establishes the barrier pool and allocation rules, but subsequent barrier selections and synchronizations are handled autonomously by the tiles according to pre-established criteria, reducing the complexity of direct host involvement while maintaining effective synchronization control through the intermediary barrier pool system.
Data Source
AI summary
A processing system comprising: a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles; and an interconnect for communicating between the tiles and connecting the subsystem to the host. The interconnect comprises synchronization logic to coordinate barrier synchronizations between a group of the tiles. The synchronization logic comprises a host sync proxy module, comprising a counter written with a number of credits by the host processor, and being configured to automatically decrement the number of credits each time one of the barrier synchronizations requiring host involvement is performed. When the number of credits in the counter is exhausted, the barrier is not released until a further write from the host to the host sync proxy module, but when the number is credits in the counter is not exhausted the barrier is released without a separate write from the host.