Host-Wireless Processor Interface for Artificial Reality Latency

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Solution Overview

Problem

Existing artificial reality systems face latency issues due to the need for continuous communication between head wearable devices and consoles, leading to potential motion sickness and degraded user experience from judder caused by latency in rendering virtual environments.

Innovation Solution

A system comprising a host processor and a wireless processor that manage power states to reduce latency by transitioning between active and sleep states based on frame times, using indicators to synchronize clock synchronization and optimize power efficiency during artificial reality sessions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous communication is maintained between host processor and wireless processor, then data transmission reliability is improved, but power consumption increases and latency occurs

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system transitions between active and sleep states periodically based on frame times. The host processor and wireless processor enter sleep state after completing data transmission for a frame, then wake up at the next frame time to resume communication. This periodic activation reduces power consumption while maintaining reliable data transmission during active periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system performs preliminary synchronization of frame times and wake-up schedules before entering sleep state. The host processor provides indicators to the wireless processor about upcoming frame times and wake-up requirements, ensuring that both processors are ready to resume communication at the correct time without data loss or transmission errors.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If processors enter sleep state to reduce power consumption, then energy efficiency is improved, but synchronization complexity increases

Engineering Contradiction:
Improveenergy efficiencyVSAvoidsynchronization complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The host processor provides feedback indicators to the wireless processor about frame completion and wake-up timing requirements. These indicators include information about when the next frame will start and when the wireless processor should wake up, allowing the wireless processor to synchronize its sleep-wake cycle with the host processor without requiring complex bidirectional negotiation protocols.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Frame time synchronization acts as an intermediary mechanism between the host processor and wireless processor. Rather than requiring direct complex synchronization protocols between the two processors, the frame time structure serves as a common reference that both processors can independently align to, simplifying the synchronization process while maintaining energy efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If frame time is reduced to minimize latency, then responsiveness is improved, but processing time per frame decreases

Engineering Contradiction:
ImprovelatencyVSAvoidprocessing time per frame
Core Design Contradiction:
Loss of timeVSDuration of action of moving object

Solution Approach 1:

Data transmission and processing are completed in advance during the active state before the frame time expires. The host processor prepares and transmits the entire frame of data to the wireless processor within the allocated frame time, ensuring that the next frame can start immediately without delay. This preliminary completion of processing minimizes latency while maintaining adequate processing time within each frame.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11314320B2Interface between host processor and wireless processor for artificial reality
Publication Date: 2022.04.26 META PLATFORMS TECHNOLOGIES LLC
  • US11314320B2 patent drawing
  • US11314320B2 patent drawing
  • US11314320B2 patent drawing

AI summary

Disclosed herein are devices and methods related to an interface between a host processor and a wireless processor of a first device for maintaining an artificial reality session with a second device. In one aspect, the host processor is configured to provide data of the artificial reality session to the wireless processor, and the wireless processor is configured to transmit the data to the second device through a wireless medium. In one aspect, the host processor is configured to provide an indicator indicating an end of transmission of the data, to the wireless processor, to cause the wireless processor to transmit the indicator to the second device through the wireless medium, and to cause the host processor and the wireless processor to enter a sleep state in response to transmission of the indicator. The indicator may cause the second device to enter the sleep state.