Hot De-latch Integrated Circuit Parasitic SCR Control
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Solution Overview
Problem
Advanced-technology CMOS and bipolar integrated circuits are susceptible to single-event latch-up (SEL) due to parasitic bipolar transistors forming a silicon controlled rectifier (SCR), which can cause a low impedance path and disable the IC, potentially leading to permanent damage and loss of functionality.
Innovation Solution
A hot de-latch system and method that reduces the voltage supplied to the IC from a normal operating voltage to a de-latch voltage to de-activate the parasitic SCR without de-powering the IC, using a control block to initiate a control pulse that lowers the voltage below a data retention level for a specific duration, allowing the IC to return to normal operation without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage is reduced to de-latch the parasitic SCR, then the latch-up condition is resolved and IC functionality is restored, but data loss may occur if voltage drops below data retention level
Solution Approach 1:
The system dynamically adjusts the voltage supply to the IC, transitioning from normal operating voltage to a reduced de-latch voltage that is sufficient to deactivate the parasitic SCR while maintaining it above the data retention threshold. This dynamic voltage control allows the system to resolve the latch-up condition without causing data loss.
Solution Approach 2:
The invention changes the voltage parameter from normal operating levels to a specific de-latch voltage level that falls within a critical range - low enough to stop the latch-up current but high enough to preserve data integrity. This precise parameter adjustment resolves the contradiction between restoring functionality and preventing data loss.
2Reliability
If voltage is completely removed to de-latch the SCR, then the latch-up is cleared, but the IC must be re-powered and data is lost
Solution Approach 1:
Instead of completely removing power from the IC (excessive action), the system applies a partial voltage reduction to the de-latch voltage level. This partial action is sufficient to clear the latch-up condition while maintaining power to the IC, thereby avoiding the need for re-powering and eliminating time loss.
Solution Approach 2:
The invention maintains continuous power supply to the IC during the de-latch process by keeping the voltage above the retention threshold. This continuity of useful action ensures the IC remains powered and operational throughout the de-latch sequence, preventing data loss and eliminating re-power time.
3Loss of information
If normal operating voltage is maintained during latch-up, then the IC remains powered, but the parasitic SCR continues to conduct causing potential damage
Solution Approach 1:
The system changes the voltage parameter from normal operating level to a reduced de-latch voltage level that fundamentally alters the electrical characteristics of the parasitic SCR, causing it to deactivate. This parameter change simultaneously achieves data retention (by maintaining voltage above threshold) and eliminates harmful latch-up current.
Solution Approach 2:
The invention implements dynamic voltage control that responds to the latch-up condition by adjusting the supply voltage to a specific de-latch level. This dynamic adjustment maintains the delicate balance between preserving data (requiring sufficient voltage) and stopping harmful current (requiring reduced voltage).
Data Source
AI summary
A system and method is provided for hot de-latch of a parasitic device in an integrated circuit (IC) that restores the IC to normal operation without de-powering the IC or resulting in a loss of data. In one embodiment the method, includes reducing a voltage supplied to at least a portion of the IC from a normal operation voltage to a de-latch voltage for a time to de-latch the parasitic device without de-powering the IC. Other embodiments are also disclosed.