Hybrid Orientation Technology for High-Voltage Transistors
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Solution Overview
Problem
Conventional CMOS circuits face limitations in achieving high hole and electron mobilities, particularly in forming higher voltage devices, as they often rely on a single crystalline orientation, which restricts the development of efficient semiconductor devices for mixed-signal analog applications.
Innovation Solution
The integration of hybrid orientation technology (HOT) with selective epitaxy, where a semiconductor wafer combines (100) and (110) crystalline orientations, along with epitaxial layers of silicon germanium, enables the formation of PMOS and NMOS devices with improved mobilities, allowing for higher voltage operations by leveraging different material orientations and properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS circuits use a single crystalline orientation substrate, then manufacturing is simpler, but hole and electron mobilities are limited
Solution Approach 1:
The substrate is segmented into different crystalline orientation regions - specifically (100) orientation regions for NMOS devices and (110) orientation regions for PMOS devices. This segmentation allows each device type to benefit from the optimal crystalline orientation for its carrier type, thereby improving both hole and electron mobilities while managing complexity through functional zoning.
Solution Approach 2:
Different local regions of the substrate are assigned different crystalline orientations tailored to specific device requirements. The (100) orientation is applied locally where NMOS devices require high electron mobility, while (110) orientation is applied locally where PMOS devices require high hole mobility. This local quality approach optimizes performance in each region without requiring the entire substrate to have complex multi-orientation structure.
2Reliability
If hybrid orientation technology is used to improve mobilities, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The crystalline orientations are predetermined and pre-established in the substrate before device fabrication begins. The substrate is manufactured with specific (100) and (110) orientation regions already in place, allowing subsequent fabrication processes to proceed using standard techniques without needing to dynamically adjust or reorient materials during manufacturing. This preliminary preparation simplifies the overall fabrication process despite the complex substrate structure.
3Reliability
If deep sub-micron techniques are used to achieve higher voltage devices, then device voltage capability improves, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of relying on deep sub-micron dimensional scaling to achieve higher voltage capability, the invention changes the fundamental parameter of crystalline orientation. By selecting appropriate orientations ((100) for NMOS, (110) for PMOS), the devices achieve improved voltage operation and carrier mobilities through material property optimization rather than dimensional reduction. This parameter change allows higher voltage operation without requiring complex deep sub-micron fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances both hole and electron mobilities, enabling the creation of higher voltage devices with improved transistor performance, reduced die sizes, and lower costs, suitable for mixed-signal analog applications without relying on deep sub-micron techniques.
Implementation Method 1
selective epitaxy, where a semiconductor wafer combines (100) and (110) crystalline orientations, along with epitaxial layers of silicon germanium
Data Source
AI summary
A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.