Programmable Hot Plug Controller for Multidrop Serial Bus

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Solution Overview

Problem

Multidrop serial buses in mobile communication devices face challenges in maintaining resilience during hot-join and hot-plugin events, which can disrupt ongoing communication and lead to signaling errors.

Innovation Solution

A video processing circuit with a bus interface configured to detect sequentially occurring signaling states on a multidrop differential serial link, transitioning from low-power to high-speed mode only when specific duration criteria are met, and returning to low-power mode when these criteria are not fulfilled, thereby managing transitions and minimizing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the bus interface circuit transitions to high-speed mode during hot-plugin events, then data transmission speed is improved, but signaling errors occur due to premature mode switching

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignaling accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system performs preliminary detection of signaling states and their durations before transitioning to high-speed mode. The detector circuits monitor the serial link for a sequence of signaling states (e.g., LP-111, LP-001, LP-000) and verify that each state persists for a minimum required duration, ensuring the target device is fully powered and ready before enabling high-speed data transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where detector circuits continuously monitor the signaling states on the serial link and provide information to control logic. This feedback enables the system to adjust its operation by confirming that signaling states meet minimum duration criteria before mode transition, and to detect hot-plugin events by identifying unexpected state sequences.

Inventive Principle:
Principle #23Feedback

2Reliability

If the system implements detection of signaling state durations, then reliability during hot-plugin events is improved, but device complexity increases due to additional detector circuits and control logic

Engineering Contradiction:
Improvecommunication stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detector circuits and control logic are designed to serve multiple functions: detecting signaling states, measuring their durations, identifying hot-plugin events, and controlling mode transitions. This multi-functionality reduces the need for separate dedicated circuits for each task, thereby limiting the increase in overall device complexity while maintaining improved reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the bus interface circuit remains in low-power mode during hot-join events, then signaling errors are reduced, but data transmission efficiency decreases

Engineering Contradiction:
Improvesignaling accuracyVSAvoiddata transmission efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically transitions between low-power and high-speed modes based on real-time detection of signaling state sequences and durations. During normal operation, the system switches to high-speed mode for efficient data transmission. During hot-plugin or hot-join events, the system remains in low-power mode until proper signaling is confirmed, thereby adapting its performance characteristics to match the operational context and optimizing both reliability and efficiency.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12093116B2Programmable hot plug-in controller for a multidrop differential serial bus
Publication Date: 2024.09.17 QUALCOMM INC
  • US12093116B2 patent drawing
  • US12093116B2 patent drawing
  • US12093116B2 patent drawing

AI summary

A video processing circuit has a bus interface circuit configured to communicatively couple the video processing circuit to an imaging device over a multidrop differential serial link; detector circuits configured to detect sequentially occurring signaling states of the multidrop differential serial link, the sequentially occurring signaling states preceding a transition of the bus interface circuit from a low-power mode to a high-speed mode; and a controller configured to: cause the bus interface circuit to receive data transmitted over the multidrop differential serial link in the high-speed mode when a duration of each signaling state in the sequentially occurring signaling states exceeds a minimum duration defined for the each signaling state; and cause the bus interface circuit to return to the low-power mode when one signaling state of the sequentially occurring signaling states does not exceed a corresponding minimum duration defined for the one signaling state.