HOT Substrate Boundary Morphology Reduction via SPE
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Solution Overview
Problem
Conventional hybrid orientation technology (HOT) methods for integrated circuits introduce discontinuities and defects at the boundaries between (100)-oriented and (110)-oriented silicon regions, making them unsuitable for high transistor density circuits and imposing limits on transistor scaling, especially in advanced nodes like the 65 nanometer technology and beyond.
Innovation Solution
A method involving a direct silicon bonded substrate with a (110)-oriented silicon layer on a (100)-oriented silicon wafer, using a partially absorbing amorphization hard mask and ion implantation to amorphize regions, followed by solid phase epitaxial recrystallization, which reduces lateral spread and eliminates template recrystallization into NMOS regions, allowing for precise formation of (100)- and (110)-oriented silicon regions without introducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional amorphization and templated recrystallization (ATR) is used to form hybrid orientation regions, then (100)- and (110)-oriented silicon regions are formed for NMOS and PMOS transistors, but discontinuities and defects (morphology) are introduced at the lateral boundaries between regions
Solution Approach 1:
The patent performs recrystallization before the shallow trench isolation (STI) process, which allows the boundary morphology to be established early in the fabrication sequence. This preliminary action enables subsequent processes to work around or accommodate the boundary region without introducing additional defects, thereby maintaining transistor performance while achieving the desired crystal orientation separation.
2Productivity
If conventional ATR with recrystallization before STI is used, then (100)- and (110)-oriented silicon regions are formed, but the morphology region is not suitable for MOS transistors and proscribes conventional ATR for high transistor density circuits
Solution Approach 1:
By performing recrystallization before STI, the patent establishes the crystal orientation boundaries early, allowing the morphology region to be accounted for in the layout design. This enables high transistor density circuits to be implemented by carefully placing transistors in regions with appropriate crystal orientations while accounting for the boundary morphology width.
3Reliability
If conventional ATR with recrystallization after STI is used, then (100)- and (110)-oriented silicon regions are formed, but stable defects are introduced at STI boundaries requiring anneals over 1250 C
Solution Approach 1:
The patent performs recrystallization before the STI process, which prevents the formation of stable defects at STI boundaries that would require high-temperature annealing. By establishing the crystal orientation boundaries before STI, the subsequent isolation process does not create additional defects, eliminating the need for anneals over 1250 C and preserving dimensional integrity for deep submicron lithography.
4Productivity
If conventional ATR is used, then hybrid orientation regions are formed, but unacceptable limits are imposed on transistor scaling
Solution Approach 1:
By performing recrystallization before STI, the patent establishes the crystal orientation boundaries early in the fabrication process. This allows for more precise control over the boundary morphology and enables tighter transistor spacing, thereby removing unacceptable limits on transistor scaling and allowing continued scaling to smaller technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of integrated circuits with optimized carrier mobility for NMOS and PMOS transistors, allowing for closer transistor placement, reduced manufacturing costs, and enhanced transistor scaling capabilities, while maintaining dimensional integrity and performance.
Implementation Method 1
an amorphizing ion implant which completely amorphizes the (110)-oriented silicon layer in NMOS regions and amorphizes the silicon in the top portion of the DSB layer under the partially absorbing amorphization hard mask layer
Implementation Method 2
A solid phase epitaxial (SPE) process is performed in which (100)-oriented silicon is formed in the NMOS regions using the (100)-oriented silicon in the wafer substrate for a seed layer
Implementation Method 3
Lateral spread of the boundary region between the DSB layer and the SPE layer is reduced by the presence of the amorphized silicon in the PMOS regions, which recrystallizes to form (110)-oriented silicon using the DSB silicon for a seed layer
Data Source
AI summary
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.