Hot-Swap Power Controller Sequenced Power-Good Signals
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Solution Overview
Problem
Existing power controllers generate a single 'power-good' signal that may not accurately reflect the operational readiness of electronic components, leading to potential errors during startup and abrupt power termination, which can hinder proper shutdown routines.
Innovation Solution
A power controller system using a two-bit signal (PWRGD and DLY_PWRGD) to indicate power stability and readiness, with a delayed signal allowing components to reach a steady state before authorization and providing time for proper shutdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power-good signal is generated to indicate power is supplied, then the signal generation is simple, but the operational readiness of the card cannot be accurately reflected
Solution Approach 1:
The single power-good signal is segmented into two distinct signals: PWRGD (power good) and DLY_PWRGD (delayed power good). PWRGD indicates that power is being supplied to the card, while DLY_PWRGD indicates that the card is fully operational and ready for communication. This segmentation allows the system to distinguish between different power states and operational readiness levels.
2Speed
If power is instantly removed when a fault condition is detected, then the response time is fast, but the card cannot properly shut down
Solution Approach 1:
Before completely removing power from the card, the system first deasserts the DLY_PWRGD signal to initiate a controlled shutdown sequence. This preliminary action allows the card to begin its shutdown routine (such as saving data) before power is completely removed, ensuring reliable shutdown while maintaining fast response to fault conditions.
3Productivity
If the card is used immediately after power-good signal is asserted, then the system responsiveness is high, but errors may occur during the card's startup period
Solution Approach 1:
The system introduces a delayed power-good signal (DLY_PWRGD) that is asserted after a predetermined delay period (e.g., 100 milliseconds) following the initial power-good signal. This delay allows voltage regulators to reach steady state and capacitors to fully charge before the card is authorized for communication. The system maintains responsiveness by using the immediate PWRGD signal for power indication while the delayed DLY_PWRGD signal controls communication authorization.
Data Source
AI summary
A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.