Howard Cascade Inter-Chip Communication via Shared Memory Queues
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Solution Overview
Problem
Current multiprocessor systems on a chip (MPSoCs) face inefficiencies in inter-core and inter-chip communication, particularly in coordinating shared memory access and message transmission across multiple processor nodes, leading to increased memory access times and potential blocking issues.
Innovation Solution
The implementation of a Howard Cascade architecture, which utilizes a switch fabric for inter-core and inter-chip communication, including shared memory configurations with input queues, allows for coordinated communication between multiple System on a Chip (SoC) nodes, eliminating the need for memory locking/unlocking and preventing blocking by using a tree broadcast all-to-all exchange mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional shared memory access coordination is used in multiprocessor systems, then memory access control is implemented, but memory access time increases and blocking issues occur
Solution Approach 1:
The patent introduces a message queue as an intermediary mechanism between processor nodes and shared memory. Instead of direct memory access requiring coordination and locking, messages are queued and transmitted through the message queue interface, eliminating the need for memory locking/unlocking operations and reducing access time while maintaining reliable access control.
Solution Approach 2:
The patent replaces the traditional mechanical locking/unlocking mechanism for memory access coordination with a software-based message queue system. This substitution eliminates the blocking issues and time delays associated with hardware-level memory locking, allowing concurrent access without interference while maintaining access control integrity.
2Reliability
If traditional inter-core communication methods are used, then communication between cores is established, but communication efficiency decreases and blocking occurs
Solution Approach 1:
The patent segments the communication system into independent message queues for each processor node, allowing parallel message transmission without interference. This segmentation enables multiple cores to communicate simultaneously through their respective queues, eliminating blocking issues while maintaining reliable communication between all core pairs.
Solution Approach 2:
The message queue mechanism enables continuous message transmission between processor nodes without interruption or blocking. Messages are queued and transmitted in a continuous flow, allowing communication to proceed without the start-stop pattern caused by traditional coordination protocols, thereby improving overall communication efficiency.
3Reliability
If memory locking/unlocking mechanisms are used for coordination, then access control is maintained, but system blocking increases
Solution Approach 1:
The message queue serves as an intermediary that handles all coordination and access control requirements, eliminating the need for memory locking/unlocking mechanisms. The queue manages message transmission between nodes without requiring any node to block or acquire locks, thereby maintaining access control while completely eliminating system blocking.
Solution Approach 2:
Each processor node independently manages its own message queue without requiring coordination or locking with other nodes. The self-service nature of individual queue management eliminates inter-node dependencies that cause blocking, while the queue structure itself provides the necessary access control and coordination functionality.
Data Source
AI summary
A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication. The parallel processing system includes a plurality of chips, each formed as an MPSoC, and implements communication between the chips using shared memory.