HP Standard Cell Layout With Wider M0 Output Paths
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Solution Overview
Problem
The scaling of transistors in integrated circuits leads to increased parasitic resistance in standard cells due to shrinking metal wires and vias, especially in high-performance (HP) standard cells with backside power delivery, which affects output node resistance and frequency performance.
Innovation Solution
Implementing wider M0 track patterns with specific shapes, wider M1 straps, and larger viaT and via0 sizes on output nodes, along with backside power delivery networks, to reduce output resistance and improve frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard cell height is reduced to increase the number of memory or logic devices on a semiconductor chip, then device density is improved, but parasitic resistance in metal wires and vias increases
Solution Approach 1:
The patent applies local quality by making the M0 metal trace width variable along its length. Specifically, the M0 trace is wider in the middle region (away from cell boundaries) and narrower near cell boundaries. This localized variation optimizes the trace to carry higher currents in the middle while maintaining proper spacing at boundaries, thereby reducing parasitic resistance in critical regions without increasing overall cell height.
Solution Approach 2:
The patent changes the geometric parameter of the M0 trace width along its length. The M0 trace width transitions from a uniform width to a non-uniform width profile, being approximately 1.5 times wider in the middle region compared to the regions near cell boundaries. This parameter change reduces resistance in high-current regions while maintaining manufacturing feasibility and proper spacing.
2Power
If transistors are made stronger to improve performance, then transistor drive capability is improved, but the relative contribution of parasitic resistance from metal wires and vias increases
Solution Approach 1:
The patent addresses the relative parasitic resistance issue by applying local quality to the M0 trace geometry. The widened middle section of the M0 trace provides a lower-resistance path for the increased current driven by stronger transistors, thereby reducing the relative impact of parasitic resistance in the interconnect while maintaining the enhanced transistor drive capability.
3Object-affected harmful factors
If M0 trace width is increased to reduce resistance, then parasitic resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent manages manufacturing complexity by implementing a controlled parameter change in the M0 trace width. The width variation follows a specific pattern (wider in the middle, narrower at boundaries) that can be integrated into existing manufacturing processes. The design maintains manufacturability by using reasonable width ratios (approximately 1.5x) and smooth transitions that are compatible with standard lithography and etching processes.
Data Source
AI summary
A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.