HPA Bias Circuit With Buffer Offset for Stable Low-Power Gain
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Solution Overview
Problem
Multistage power amplifiers in wireless communication devices experience significant variations in control voltage-output power characteristics due to temperature and process variations, leading to difficulties in controlling output power at low levels and high sensitivity to bias settings.
Innovation Solution
A bias circuit design incorporating a linear amplifier, diode-connected FETs, and a buffer amplifier with threshold voltage offset, along with a resistor network to control the gate voltage of a second FET, reduces gain variation and suppresses sensitivity to bias voltage, using current drivability coefficients to minimize undesired components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional multistage bias circuit is used, then the circuit structure is simple, but the control voltage-output power characteristic varies drastically near the threshold voltage and shows high sensitivity to bias settings
Solution Approach 1:
A buffer amplifier is introduced as an intermediary component between the bias voltage input and the power amplifier stages. This buffer amplifier includes a threshold voltage offset that prevents the bias circuit from operating in the high-sensitivity threshold region, thereby stabilizing the control voltage-output power characteristic while maintaining circuit simplicity
Solution Approach 2:
The buffer amplifier is designed with a threshold voltage offset parameter that shifts the operating point away from the problematic threshold region. By changing the voltage parameter through the buffer's transfer characteristic, the circuit achieves stable control characteristics without increasing overall structural complexity
2Power
If the bias voltage is increased to improve output power control, then the output power increases, but the gain variation becomes excessive and control becomes difficult at low power levels
Solution Approach 1:
The buffer amplifier acts as a mediator that transforms the input bias voltage into a stabilized gate voltage for the power amplifier. This transformation ensures that output power can be controlled across the full range while preventing excessive gain variation, making control easier at all power levels including low power
Solution Approach 2:
The threshold voltage offset in the buffer amplifier provides beforehand cushioning by preventing the circuit from entering the high-gain-variation region near the threshold. This protective mechanism ensures stable control characteristics are maintained before problems can occur
3Use of energy by moving object
If the multistage amplifier operates near the transistor threshold voltage, then the circuit efficiency is improved, but the sensitivity to bias settings becomes excessively high causing product variations
Solution Approach 1:
The buffer amplifier with threshold offset serves as a protective intermediary that decouples the efficiency-optimizing operating point from the sensitivity-problematic threshold region. This allows the amplifier to operate efficiently while the buffer prevents excessive bias sensitivity and product variations
Data Source
AI summary
To provide a bias circuit for gain control that can reduce gain variation at low-power output, facilitate setting of output power, and is unlikely to be affected by variation in element values and variations among products. Use in an HPA having three bias circuits serially-connected is assumed. Current of the third bias circuit is varied with a square-law characteristic. The square-law characteristic is amplified by a buffer amplifier including a linear amplifier and a peripheral circuit thereof. Output current of the third bias circuit varies depending on a current drivability coefficient of the diode-connected FET branched from the connection point between a constant current source and the linear amplifier. The output current of the third bias circuit is controlled by providing a circuit that draws a certain amount of current from the current flowing in the FET.