Host Performance Acceleration Mode for eMMC L2P Translation
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Solution Overview
Problem
The increasing capacity of eMMC storage devices leads to a significant burden on conventional management methods for logical-to-physical mapping (L2P) tables, resulting in excessive time spent on L2P translation, which hampers the performance of data reads.
Innovation Solution
Implementing a Host Performance Acceleration (HPA) mode that shifts the workload of L2P translation from the flash controller to the host side by using an HPA buffer in system memory to store L2P mapping entries, allowing direct data retrieval from the flash device without needing to access the L2P mapping table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device capacity is increased to meet growing storage demands, then the storage capacity is improved, but the time spent on L2P translation increases significantly
Solution Approach 1:
The patent extracts the L2P translation function from the flash controller to the host side. The host maintains a local L2P mapping table in its memory, allowing it to perform address translations independently without burdening the flash controller. This extraction resolves the contradiction by enabling the flash device to support larger capacities while the host handles the translation overhead, preventing translation time from becoming a bottleneck.
Solution Approach 2:
The patent implements preliminary action by having the host pre-fetch and cache L2P mapping entries in its local memory before they are needed for actual data operations. The host can proactively load mapping tables into its cache, so when data read/write operations occur, the translation is already prepared or can be quickly retrieved, significantly reducing the translation time during actual storage operations.
2Reliability
If the L2P mapping table is managed on the device side to maintain data integrity, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the L2P management functionality from the flash controller to the host system. The host becomes responsible for maintaining the L2P mapping table, handling address translations, and managing mapping updates. This extraction reduces flash controller complexity while maintaining reliability, as the host system already has the capability to manage such data structures and can leverage its existing memory management infrastructure.
Solution Approach 2:
The patent introduces a new communication protocol and data structure format as an intermediary between the host and flash controller. The host communicates L2P mapping information to the flash controller through standardized interfaces, allowing the flash controller to focus on its core storage functions while the host handles the complex L2P management. This intermediary layer maintains data integrity through standardized protocols while keeping the flash controller relatively simple.
3Speed
If the L2P translation is performed on the device side to ensure fast access, then the speed is improved, but the loss of time during translation operations increases
Solution Approach 1:
The patent implements preliminary action by having the host pre-load and cache L2P mapping entries in its local memory before data operations are initiated. The host can proactively translate addresses and prepare mapping information, so when actual data read/write operations occur, the translation is already complete or can be quickly retrieved from cache, significantly reducing the translation time during critical data access operations.
Solution Approach 2:
The patent changes the spatial dimension of L2P table storage from the flash device to the host's system memory. By moving the L2P table to a different memory dimension (host RAM instead of flash memory), the system achieves faster access speeds since the host can access its own memory much quicker than the flash controller can access flash memory, thereby improving both speed and reducing translation time.
Data Source
AI summary
The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: searching an HPA buffer in a system memory for a logical-block-address to physical-block-address (L2P) mapping entry corresponding to a logical block address (LBA); issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and does not activate an acquisition function for an L2P mapping table, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; issuing a write_multiple_block command to the flash controller to transfer a first data block to the flash controller, which includes the first L2P mapping entry; and issuing a read_multiple_block command to obtain data corresponding to the first L2P mapping entry from the flash controller.