Host Performance Booster Memory Access Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The management of accessing Flash memory devices is complex, and the insufficient storage capacity of RAM in related art solutions introduces additional problems, necessitating a novel method for access management in a Host Performance Booster (HPB) architecture that minimizes side effects.
Innovation Solution
A method involving device side table information encoding and decoding is employed, where a memory controller encodes internal information, generates address mapping control tables, and decodes partial information to determine physical addresses for data retrieval, ensuring reliable access and security in a Host Performance Booster (HPB) architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device side table information is transmitted in plain text format, then the host device can easily store and access the information, but the system becomes vulnerable to security issues and information integrity problems
Solution Approach 1:
The patent applies parameter changes by transforming the device side table information from plain text format to an encoded format before transmission to the host device. This encoding process changes the state of the information, making it secure while maintaining accessibility through the corresponding decoding procedure at the host device.
2Speed
If the host device stores complete device side table information locally, then access speed improves, but the host device requires more storage space
Solution Approach 1:
The patent extracts only the necessary encoded device side table information that is needed for HPB operations and transmits it to the host device for local storage. This extraction approach allows the host to store and access critical information locally for fast access while avoiding the need to store the entire device side table, thus optimizing the balance between access speed and storage space consumption.
3Measurement precision
If the memory controller processes all device side table information, then information accuracy is maintained, but the processing time and computational resources increase
Solution Approach 1:
The patent implements partial action by having the host device decode and process only the specific portions of the encoded device side table information that are relevant to HPB operations, rather than processing the entire device side table. This selective processing approach maintains information accuracy for the necessary data while significantly reducing the time and computational resources required compared to processing all information.
Data Source
AI summary
A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.