HPB Mode Switching for L2P Mapping Synchronization Load Balancing
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Solution Overview
Problem
Existing host performance booster (HPB) modes in computing devices suffer from performance degradation due to synchronization issues in logical-to-physical (L2P) address mapping tables, which are affected by operations executed by the host controller or memory device controller, leading to inefficient memory access transactions.
Innovation Solution
Implementing host performance booster (HPB) modes based on the availability of the host controller and memory device controller, dynamically enabling host control mode (HCM) or device control mode (DCM) to reduce the impact of other operations on L2P address mapping table synchronization, by shifting the burden of determining inactive and active regions to the available controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If L2P address mapping table synchronization is performed during controller busy periods, then memory access transactions can proceed, but performance degradation occurs due to synchronization issues
Solution Approach 1:
The patent implements dynamic mode switching between host control mode and device control mode based on the availability of the host controller and memory device controller. This dynamic adaptation allows the system to select the optimal control mode at any given time, resolving the contradiction by making the synchronization process flexible rather than static, thereby maintaining both productivity and reliability under varying operational conditions
Solution Approach 2:
The patent changes the operational parameter of controller control mode (from fixed to variable) based on the availability state of controllers. By monitoring controller availability and switching between host control mode and device control mode, the system optimizes L2P address mapping table synchronization performance, resolving the contradiction between maintaining synchronization reliability and achieving high memory access speed
2Productivity
If host controller manages L2P address mapping table during busy periods, then memory access can be maintained, but performance degrades due to load on host controller
Solution Approach 1:
The system dynamically switches control responsibility between host controller and memory device controller based on availability. When host controller is busy, control transitions to device control mode where the memory device controller manages L2P address mapping table synchronization, thereby reducing host controller load while maintaining operation performance
Solution Approach 2:
The patent extracts the L2P address mapping table synchronization management function from the host controller and transfers it to the memory device controller under device control mode. This extraction reduces the burden on the host controller during busy periods, allowing it to focus on other critical operations while maintaining overall system performance
3Device complexity
If device control mode is enabled during host controller availability, then host controller load is reduced, but synchronization issues may occur
Solution Approach 1:
The system continuously monitors the availability state of both host controller and memory device controller, using this feedback to determine when to switch between host control mode and device control mode. This feedback mechanism ensures that device control mode is only enabled when appropriate, maintaining synchronization reliability while reducing host controller load
Solution Approach 2:
The control mode dynamically adapts based on real-time availability monitoring. The system transitions between host control mode and device control mode based on controller availability, ensuring that synchronization reliability is maintained by only using device control mode when the memory device controller is available and capable of handling synchronization tasks
Data Source
AI summary
Methods that may be performed by a host controller of a computing device for host performance booster (HPB) mode management. Embodiments may include enabling an HPB mode based on availability of the host controller and availability of a memory device controller. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a device control mode in response to an operating state of the host controller being busy and an operating state of the memory device controller being available. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a host control mode in response to the operating state of the host controller being available and the operating state of the memory device controller being busy.