Host Performance Booster Read Buffer Table for Variable Data Sizes
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Solution Overview
Problem
Current Host Performance Booster (HPB) protocols primarily optimize reads of 4K data units, leaving room for improvement in random read performance for larger data sizes, as they do not efficiently handle reads greater than 4K.
Innovation Solution
The implementation of an encoded HPB entry in a read command that includes both the Physical Block Address (PBA) and run length, stored in an HPB read buffer table within the host device, allowing for optimized reads of varying data sizes by referencing entries in a write buffer table when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the HPB protocol uses 8-byte entries for each 4K logical address, then the random read performance for 4K data units is improved, but the read performance for larger data sizes greater than 4K is not optimized
Solution Approach 1:
The HPB entry is segmented into multiple fields: LBA field, PBA field, and run length field. This segmentation allows the system to handle different read sizes efficiently by combining multiple 4K units based on the run length value, thus optimizing reads for both 4K and larger data sizes.
Solution Approach 2:
The HPB entry structure is designed to be universal, supporting both 4K reads and larger reads greater than 4K through the run length field. The same 8-byte entry format serves multiple functions by indicating different numbers of 4K units to read, eliminating the need for separate optimization mechanisms.
2Speed
If a small cache is kept in RAM on the data storage device, then the random read performance is improved, but the random range supported is limited due to RAM constraints
Solution Approach 1:
The HPB cache table is extracted from the data storage device and placed in the host device's memory. This extraction allows the host to utilize its own memory resources for caching, thereby expanding the supported random range without being constrained by the limited RAM on the storage device.
Solution Approach 2:
The caching architecture shifts from device-side caching to host-side caching, representing a dimensional change in where the cache resides. This allows leverage of the host's typically larger memory capacity to support a broader random read range.
3Measurement precision
If the HPB approach provides physical block address for each 4K unit, then the precision of address translation is improved, but the efficiency for reads greater than 4K is reduced due to lack of run length information
Solution Approach 1:
The LBA, PBA, and run length information are merged into a single HPB entry structure. This combination maintains precise address translation through the LBA-PBA mapping while simultaneously providing run length information to optimize reads of varying sizes, including reads greater than 4K.
Solution Approach 2:
The HPB entry includes a run length parameter that changes based on the read size requirements. This parameter allows the system to maintain precise address translation while adapting the read efficiency for different data sizes by specifying how many 4K units should be read in sequence.
Data Source
AI summary
Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.