HPC Data Path Segmentation for I/O Bottleneck Resolution
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Solution Overview
Problem
High-performance computing (HPC) systems face inefficiencies in data input/output performance, resilience, and energy efficiency due to the shared data paths for computational and storage operations, which can lead to bottlenecks and suboptimal resource utilization.
Innovation Solution
The proposed architecture separates data paths for computational data exchange between nodes from those used for obtaining and storing work units, employing a compute fabric for data parallelism and local data fabrics for bulk data management, allowing for optimized routing and 'zero copy' data access, thereby improving performance and resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared data paths are used for both computational data exchange and bulk data management, then device complexity is reduced, but I/O performance deteriorates due to bottlenecks
Solution Approach 1:
The patent divides the data path infrastructure into two separate networks: a compute fabric for computational data exchange between nodes, and a data fabric for bulk data management operations. This segmentation allows each network to be optimized for its specific function, eliminating the bottlenecks that occur when both types of traffic share a single network infrastructure.
2Device complexity
If shared data paths are used for computational and storage operations, then system simplicity is maintained, but resource utilization becomes suboptimal
Solution Approach 1:
By segmenting the network into compute fabric and data fabric, each network can be independently optimized and scaled according to specific workload requirements. The compute fabric handles computational traffic while the data fabric handles bulk data operations, allowing flexible resource allocation and improved overall system adaptability.
Solution Approach 2:
The patent introduces a data node as an intermediary component that manages the interface between external bulk data storage and the compute nodes. This intermediary handles bulk data operations through the data fabric, preventing direct interference with computational operations on the compute fabric, thereby improving resource utilization efficiency.
3Device complexity
If single data path architecture is used, then system simplicity is maintained, but energy efficiency deteriorates due to unnecessary data transmission
Solution Approach 1:
The separation of compute fabric and data fabric enables localized data access through the data node's memory for compute nodes, eliminating the need for frequent long-distance data transmissions across the entire network. This reduces energy consumption associated with data transmission while maintaining system simplicity through modular architecture.
Solution Approach 2:
The data node acts as an intermediary that caches bulk data in local memory, allowing compute nodes to access frequently needed data locally rather than transmitting it repeatedly across the network. This intermediary caching mechanism significantly reduces energy consumption from network transmissions while maintaining architectural simplicity.
Data Source
AI summary
A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.