Memory Mapping Algorithm for HPC Systems

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Solution Overview

Problem

High-performance computing (HPC) systems face challenges in automatically configuring memory in non-uniform memory access (NUMA) systems when the total memory exceeds the addressing capabilities of the processors, requiring manual expertise and trial-and-error to balance memory access and performance.

Innovation Solution

An algorithm that maps memory based on the number of nodes, amount of volatile memory, and I/O devices, prioritizing the number of mapped nodes, I/O nodes, I/O memory, and total memory, to optimize memory layout and access in HPC systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual memory configuration is used in HPC systems, then memory access optimization can be achieved, but system complexity and operational difficulty increase significantly

Engineering Contradiction:
Improvememory access optimizationVSAvoidmanual configuration complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system performs self-configuration of memory addressing by automatically detecting nodes, I/O devices, and memory resources. The algorithm autonomously determines optimal memory layouts without requiring manual operator intervention, thereby maintaining optimization reliability while dramatically improving ease of operation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically adjusts memory addressing parameters based on detected system configuration. By automatically modifying addressing bit allocations and memory map parameters according to the actual hardware setup, the system achieves optimized memory access while eliminating manual configuration complexity.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If more memory resources are added to HPC nodes, then computing capacity increases, but addressing limitations are reached more quickly

Engineering Contradiction:
Improvetotal memory capacityVSAvoidaddressing configuration complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system implements dynamic memory addressing configuration that adapts to the actual hardware setup. Rather than using fixed addressing schemes, the algorithm dynamically allocates addressing bits and configures memory maps based on the detected number of nodes, I/O devices, and memory resources, allowing flexible expansion without increasing configuration complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary detection and configuration before memory addressing is established. By automatically detecting all nodes, I/O devices, and memory resources at system initialization, the algorithm pre-configures optimal addressing schemes, thereby accommodating larger memory capacities without increasing operational complexity.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If automatic memory mapping algorithm is implemented, then ease of operation improves, but system complexity increases due to algorithm requirements

Engineering Contradiction:
Improveautomatic configuration capabilityVSAvoidmemory mapping algorithm complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent introduces a memory mapping algorithm as an intermediary layer between the hardware resources and the operating system. This intermediary automatically handles the complex tasks of detecting nodes, I/O devices, and memory resources, then translates them into optimal addressing schemes, thereby improving ease of operation while containing algorithmic complexity in a dedicated module.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9176669B2Address resource mapping in a shared memory computer system
Publication Date: 2015.11.03 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9176669B2 patent drawing
  • US9176669B2 patent drawing
  • US9176669B2 patent drawing

AI summary

An algorithm for mapping memory and a method for using a high performance computing (“HPC”) system are disclosed. The algorithm takes into account the number of physical nodes in the HPC system, and the amount of memory in each node. Some of the nodes in the HPC system also include input/output (“I/O”) devices like graphics cards and non-volatile storage interfaces that have on-board memory; the algorithm also accounts for the number of such nodes and the amount of I/O memory they each contain. The algorithm maximizes certain parameters in priority order, including the number of mapped nodes, the number of mapped I/O nodes, the amount of mapped I/O memory, and the total amount of mapped memory.