HPC Screening for Non-Silicon TFT Material Optimization
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Solution Overview
Problem
The development of metal-based semiconductor materials for thin film transistors (TFTs) in display applications faces challenges due to their sensitivity to composition, deposition parameters, and interactions with adjacent materials, requiring extensive empirical optimization and evaluation of a vast composition and parameter space, which is time-consuming and costly.
Innovation Solution
The application of High Productivity Combinatorial (HPC) techniques for processing site-isolated regions on a substrate, allowing for the simultaneous evaluation of multiple materials and process conditions, reducing the need for numerous experiments by creating gradients in material properties across the substrate, and optimizing deposition parameters efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If comprehensive evaluation of the entire composition range and deposition parameter space is performed, then material performance optimization is improved, but the number of experiments required increases to thousands or millions
Solution Approach 1:
The patent segments the composition space and parameter space into discrete levels, creating a hierarchical evaluation structure where not all combinations are tested exhaustively. This segmentation allows systematic exploration of the material space while reducing the total number of required experiments from thousands or millions to a manageable number through structured sampling and prioritization.
Solution Approach 2:
The patent systematically varies composition parameters and deposition parameters across defined levels, evaluating material performance at different parameter combinations. By changing parameters in a structured manner rather than exhaustively testing all possibilities, the method achieves comprehensive optimization with reduced experimental burden.
2Reliability
If metal-based semiconductor materials are used to replace a-Si, then mobility and ON/OFF current ratios are improved, but sensitivity to composition and deposition parameters increases
Solution Approach 1:
The patent addresses the sensitivity issue by systematically studying and optimizing composition parameters and deposition parameters for metal-based semiconductor materials. Through structured parameter variation and evaluation, the method identifies optimal parameter ranges and combinations that achieve high mobility and ON/OFF current ratios while managing the inherent sensitivity of these materials.
Solution Approach 2:
The patent employs feedback mechanisms where material performance results from previous experiments inform subsequent experimental design. By using performance data to guide further parameter optimization, the method efficiently navigates the complex parameter space of metal-based semiconductors, reducing the impact of their sensitivity to composition and deposition conditions.
3Reliability
If empirical optimization is performed for metal-based semiconductor materials, then material performance is improved, but development time and cost increase
Solution Approach 1:
The patent segments the empirical optimization process into structured evaluation stages with defined composition levels and parameter levels. This segmentation transforms the traditional time-consuming empirical approach into a more efficient systematic process, reducing development time and cost while maintaining performance optimization.
Solution Approach 2:
The patent implements systematic parameter changes across defined levels for composition and deposition conditions, replacing random or trial-and-error empirical optimization. This structured approach to parameter variation accelerates the optimization process, achieving material performance improvement with reduced development time and cost.
Data Source
AI summary
Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.