HPC Platform Power Throttling via System and Tray BMC Coordination

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High Performance Computing (HPC) platforms face challenges in managing power consumption efficiently, particularly when hardware accelerators contribute significantly to power excursions, leading to ineffective throttling strategies that impact overall performance.

Innovation Solution

The integration of a Baseboard Management Controller (BMC) system that includes a system BMC and a tray BMC, allowing for dynamic power throttling of managed subsystems such as GPUs and FPGAs in response to power excursion events, with the ability to prioritize workloads and manage licenses dynamically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power throttling is applied to managed subsystems during power excursion events, then total power consumption is reduced to within limits, but performance of the HPC platform deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system segments the HPC platform into multiple managed subsystems (GPUs, FPGAs, CPUs) with independent power management. The BMC independently controls power throttling for each subsystem based on their power consumption contributions, allowing selective throttling that preserves critical workloads while reducing overall power consumption during excursions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements dynamic power throttling where the BMC continuously monitors power consumption and adjusts throttling levels in real-time based on current power excursion conditions and workload priorities. This dynamic adjustment allows the system to maintain optimal performance during normal operation while rapidly responding to power events.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If deep throttling is applied to CPU during power excursions, then power consumption is reduced, but overall system performance is significantly impacted

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem performance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system applies differentiated power management policies to different subsystems based on their role and workload importance. Critical subsystems with high-priority workloads receive preferential treatment with minimal or no throttling, while non-critical subsystems undergo aggressive throttling. This local quality approach ensures that power reduction does not uniformly impact all components, preserving system performance where it matters most.

Inventive Principle:
Principle #3Local quality

3Loss of energy

If uniform throttling is applied to all managed subsystems, then power consumption is reduced, but workload priority and license management requirements are not optimized

Engineering Contradiction:
Improvepower consumptionVSAvoidworkload prioritization capability
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The BMC implements feedback mechanisms that continuously monitor power consumption contributions from each managed subsystem, workload priorities, and license management status. Based on this feedback, the system dynamically adjusts throttling policies to optimize the balance between power reduction and workload performance. High-priority workloads and licensed features receive preferential power allocation even during power excursions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12339719B2Power throttling of high performance computing (HPC) platform components
Publication Date: 2025.06.24 DELL PROD LP
  • US12339719B2 patent drawing
  • US12339719B2 patent drawing
  • US12339719B2 patent drawing

AI summary

Embodiments of systems and methods for power throttling of High Performance Computing (HPC) components are described. In some embodiments, an HPC platform may include: a system Baseboard Management Controller (BMC), and an accelerator tray comprising a tray BMC coupled to a plurality of managed subsystems and to the system BMC, where the system BMC is configured to: in response to a power excursion event, instruct the tray BMC to throttle a first managed subsystem by a first amount and to throttle a second managed subsystem by a second amount.