HPI Interconnect Architecture Layered Protocol Stack
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Solution Overview
Problem
Current interconnect architectures in computing systems face challenges in meeting the increasing demand for high-performance communication between processors and devices, particularly in server environments, where existing architectures struggle to balance performance with power efficiency and scalability.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and a coherence protocol to support cache-coherent operations, enabling efficient data transfer and management across multiple processors and devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but communication performance and bandwidth are insufficient for high-performance computing
Solution Approach 1:
The patent segments the interconnect architecture into distinct layers (physical layer, link layer, transaction layer) similar to networking protocols. This segmentation allows each layer to be optimized independently for performance while managing complexity through modular design. The physical layer handles electrical communication, the link layer manages data integrity and flow control, and the transaction layer handles higher-level communication protocols.
Solution Approach 2:
The patent transitions from traditional single-dimensional bus architectures to a multi-dimensional layered protocol stack approach. This dimensional change enables simultaneous optimization of multiple parameters (bandwidth, latency, power efficiency) across different layers, allowing the system to achieve high-performance communication while maintaining manageable complexity through hierarchical organization.
2Productivity
If multiple processors and devices are added to increase computing power, then processing capability is improved, but communication demand and power consumption increase
Solution Approach 1:
The patent implements periodic flow control mechanisms where credits are allocated and consumed in discrete units. This periodic action allows the system to manage power consumption by controlling the rate and timing of data transfers between processors and devices, enabling high-performance communication while regulating energy usage through structured, periodic credit-based flow control.
Solution Approach 2:
The patent introduces a credit-based flow control intermediary that mediates communication between multiple processors and devices. This intermediary mechanism tracks and regulates data flow, enabling efficient resource utilization across the interconnect while managing power consumption by controlling when and how data transfers occur, thus supporting scalable computing power without linear power increases.
3Productivity
If credit-based flow control is implemented, then data transfer efficiency is improved, but protocol complexity increases
Solution Approach 1:
The patent implements a universal credit-based flow control mechanism that operates across all layers of the interconnect protocol stack. This universal approach allows the same credit management principles to be applied consistently throughout the system, improving data transfer efficiency while managing protocol complexity through standardized, multi-functional credit handling that works across different communication scenarios and layers.
4Productivity
If virtual channels are added to increase bandwidth, then communication capacity is improved, but device complexity increases
Solution Approach 1:
The patent segments the communication channels into multiple virtual channels, each capable of independent data flow. This segmentation increases overall bandwidth by allowing parallel communication streams while managing complexity by confining each virtual channel to specific protocol layers, enabling high-capacity communication through structured, segmented channel management.
Data Source
AI summary
A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.