On-Chip HPM Polynomial BIST for IC Speed Grading
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Solution Overview
Problem
Conventional methods for testing and binning integrated circuits are costly and time-consuming, as they require correlating actual speed with numerous functional and AC scan patterns, and are inefficient in determining the performance of chips with varying critical paths.
Innovation Solution
Incorporating a plurality of Hardware Performance Monitors (HPM) into integrated circuits to generate performance values based on a performance function, where each term's weight is determined through machine learning from sample circuits, enabling an on-chip Built In Self Test (BIST) module to automatically bin chips into different speed grades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional functional and AC scan patterns are used to test chip performance, then the correctness and operating speed can be verified, but the testing process becomes costly and time-consuming
Solution Approach 1:
The patent implements performance monitoring circuits and HPM units during the chip design and fabrication stages, so that performance data collection begins before actual testing. This preliminary setup eliminates the need for extensive post-fabrication functional and AC scan testing, dramatically reducing testing time while maintaining measurement accuracy through the pre-configured monitoring infrastructure.
Solution Approach 2:
The patent creates simplified models or representations of chip performance through HPM units that monitor critical paths and generate performance data without requiring full functional testing. These HPM-based performance models serve as substitutes for comprehensive functional and AC scan pattern testing, reducing both time and cost while preserving essential performance verification.
2Measurement precision
If thousands of critical paths are observed to determine chip delay, then comprehensive performance data can be obtained, but the correlation becomes inefficient
Solution Approach 1:
The patent extracts only the most critical performance-determining paths from the thousands of possible critical paths using HPM units. Instead of observing all critical paths, the system identifies and monitors a small subset of paths that have the greatest impact on overall chip performance. This extraction approach maintains measurement accuracy while dramatically improving efficiency by reducing the data processing burden.
Solution Approach 2:
The patent applies different monitoring strategies to different regions or paths within the chip. HPM units are strategically placed to monitor specific critical paths with higher weights based on their impact on overall performance. This localized quality approach ensures that resources are focused on the most important performance determinants rather than uniformly monitoring all paths, thereby improving efficiency without sacrificing accuracy.
3Device complexity
If a single ROSC or duplicated critical path is used to correlate performance, then the design is simple, but it is not effective for thousands of varying critical paths
Solution Approach 1:
The patent implements HPM units that serve multiple functions: they can monitor multiple critical paths simultaneously, adapt to different chip configurations, and provide performance data for various analysis purposes. This multi-functionality allows a single HPM-based system to handle thousands of varying critical paths effectively, maintaining measurement precision without requiring separate monitoring structures for each path.
Solution Approach 2:
The patent creates a dynamic performance monitoring system where HPM units can adaptively adjust which critical paths to monitor based on real-time chip behavior and performance requirements. Rather than using a fixed single ROSC or duplicated path structure, the system dynamically selects and monitors the most relevant critical paths, ensuring accurate performance correlation even as chip operating conditions change.
Data Source
AI summary
A method of determining the performance of a chip of an integrated-circuit design comprises instantiating a plurality of HPM in the integrated-circuit design to generate the performance of the chip according to a performance function defined by a polynomial comprising a plurality of terms, wherein each term of the polynomial comprises an exponent of a value generated by a corresponding one of the plurality of HPM(s) and a corresponding coefficient, wherein the coefficients are determined through a regression process with sample chips of the integrated-circuit design having known performance, so that the performance of each chip other than the sample chips can be determined by the performance function and the values of the plurality of HPM(s) of the chip.