Hard Post Package Repair Verification in Volatile Memory

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Solution Overview

Problem

There is a lack of effective methods to verify the functionality of hard post package repair (hPPR) in memory devices, making it difficult for customers and vendors to ensure that the repair process is successful.

Innovation Solution

A system and method involving a processor, storage device, and connection device that writes and reads data from a volatile memory to perform and verify hPPR operations, comparing initial and post-repair data to determine the success of the repair process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hPPR function is implemented to repair failure rows, then production reliability is improved, but verification capability deteriorates (no way to know if repair actually works)

Engineering Contradiction:
Improveproduction reliabilityVSAvoidverification capability
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies preliminary action by pre-writing a specific data pattern (e.g., all 0s or all 1s) into the target row before the hPPR operation. This predetermined data serves as a reference for later verification, allowing the system to check whether the repair was successful by comparing post-repair read data with the expected pattern. This preliminary preparation enables subsequent verification without adding complexity to the repair process itself.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by reading back data from the repaired row and comparing it with the predetermined data pattern. This comparison provides feedback information that indicates whether the hPPR operation was successful. The feedback mechanism allows vendors and customers to verify repair effectiveness, transforming an unverified repair process into one with measurable outcomes.

Inventive Principle:
Principle #23Feedback

2Reliability

If traditional memory failure handling is used to eliminate failed devices, then product quality is maintained, but productivity deteriorates (loss of potentially repairable devices)

Engineering Contradiction:
Improveproduct qualityVSAvoidproduction yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by modifying the operational parameters of the memory device through hPPR. Instead of eliminating devices with failed rows, the system changes the state of the failed row by performing the repair operation, thereby transforming defective devices into functional ones. This parameter change approach allows devices that would traditionally be discarded to continue production, improving overall productivity while maintaining quality through verification.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If hPPR verification method is implemented with data writing and reading operations, then verification accuracy is improved, but operation complexity deteriorates

Engineering Contradiction:
Improveverification accuracyVSAvoidoperation complexity
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent applies local quality by focusing verification operations on specific target rows that have undergone hPPR, rather than requiring comprehensive verification of the entire memory array. The predetermined data pattern is written only to the relevant row, and verification is performed only on that row. This localized approach maintains high verification accuracy while reducing overall operational complexity compared to full-array verification methods.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11011251B1System and method of verifying hard post package repair and non-transitory computer readable medium
Publication Date: 2021.05.18 NAN YA TECH
  • US11011251B1 patent drawing
  • US11011251B1 patent drawing
  • US11011251B1 patent drawing

AI summary

A method of verifying a hard post package repair (hPPR) includes steps as follows. A predetermined data background is written into a partial array of a volatile memory. First data are read out from a target row of the partial array of the volatile memory. The volatile memory is commanded to perform the hPPR on the target row. The predetermined data background is written into the partial array of the volatile memory anew after the hPPR has been performed. Second data are read out from a target row of the partial array of the volatile memory. The first data are compared with the second data to verify whether the hPPR fails.