HQM Port Selection for Low-Latency Core-to-Core Messaging

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Solution Overview

Problem

The latency issues in core-to-core communications within computer processors due to varying port addresses in hardware queuing manager devices lead to performance degradation, particularly when messages follow longer data paths, causing producer cores to stall.

Innovation Solution

Implement a processor with functionality to identify and utilize a recommended port in the hardware queuing manager device based on performance metrics, such as latency, to optimize message transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If messages are transmitted through hardware queuing manager devices with multiple port addresses, then message routing flexibility is improved, but latency increases due to longer data paths

Engineering Contradiction:

Improvemessage routing flexibilityVSAvoidlatency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary profiling of hardware queuing manager devices to determine optimal port addresses before actual message transmission occurs. Test messages are sent to multiple ports during system initialization or device availability changes, and the results are stored in a data structure for future lookups, eliminating the need for real-time latency testing during message transmission

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by measuring the performance of different port addresses through test messages and using this information to update the recommended port mapping. When a hardware queuing manager device becomes unavailable or performance characteristics change, the system can re-profile and update the recommended ports based on actual measured performance data

Inventive Principle:

Principle #23Feedback

2Reliability

If producer cores wait for messages to be completed, then message processing reliability is improved, but productivity decreases due to core stalling

Engineering Contradiction:

Improvemessage processing reliabilityVSAvoidcore processing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system determines the optimal port address in advance by sending test messages to all available ports and storing the performance results. This preliminary action allows the producer core to immediately use the best-performing port for actual message transmission without needing to wait and test during operation, thereby preventing stalling while maintaining reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adapts to hardware availability by checking which hardware queuing manager devices are currently available and updating the recommended port mappings accordingly. When devices become unavailable, the system can switch to alternative ports without causing producer core stalls, maintaining both reliability and productivity

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20260064462A1Port selection for hardware queuing management device

Publication Date: 2026.03.05 INTEL CORP

AI summary

In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.