HS-NMOS Switch Gate Control With Output Slew-Rate Feedback
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Solution Overview
Problem
High-side NMOS switches require charge pumps to drive the gate terminal above the source terminal, leading to increased costs and design complexity, and existing inrush current control methods using PMOS switches result in high inrush currents due to steep voltage rises during turn-on.
Innovation Solution
A circuit arrangement with voltage and current provisioning means, including a charge pump or boost converter, and a feedback control loop to control the slew rate of the output voltage of NMOS switches, reducing the number of charge pumps required and minimizing current draw during steady-state operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If enhancement type NMOS switches are used as high-side switches, then the drain to source resistance is reduced and parasitic body diodes are simplified, but the gate terminal requires positive bias above the source terminal which necessitates charge pumps
Solution Approach 1:
A bootstrap capacitor is introduced as an intermediary energy storage element that transfers charge from the source terminal to the gate terminal during the switching cycle. The capacitor charges when the switch is off and discharges to provide the necessary gate overdrive voltage when the switch is on, eliminating the need for external charge pumps while maintaining NMOS performance advantages
2Object-affected harmful factors
If a two-phase approach with two parallel PMOS switches is used for inrush current control, then the initial inrush current is limited, but the overall switch exhibits high R DSon during the first phase which delays output voltage rise and causes high inrush current in the second phase
Solution Approach 1:
A bootstrap capacitor is pre-charged to a voltage higher than the source terminal voltage before switching begins. This preliminary energy storage enables the gate to be driven to the required voltage level immediately, allowing controlled inrush current limitation without the delays and complexity of multi-phase switching approaches
Solution Approach 2:
The gate-source voltage is dynamically adjusted through the bootstrap capacitor charging process. During the off-state, the capacitor charges to a voltage that enables controlled turn-on during the next cycle, transforming the static high R DSon problem into a dynamically controllable parameter that limits inrush current while maintaining low resistance when fully on
3Reliability
If charge pumps are used to drive NMOS gate terminals, then the switches can operate in strong inversion, but the charge pumps consume significant current during steady state operation
Solution Approach 1:
The bootstrap capacitor is charged periodically during the off-state of each switching cycle and then discharged to provide gate drive during the on-state. This periodic charge transfer provides continuous switch operation while consuming current only during brief charging intervals rather than continuously during steady-state operation
Solution Approach 2:
The bootstrap capacitor uses the existing switching action and voltage differences in the circuit to charge itself without requiring external current sources. The capacitor automatically charges from the source terminal during off-periods and discharges to the gate during on-periods, making the gate drive system self-sustaining with minimal external current consumption
Data Source
Figure 1a~1b
Figure 1c~2
Figure 3
AI summary
The present document relates to NMOS switches. In particular, the present document relates to a method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches. A circuit arrangement configured to control a first NMOS switch is described. The arrangement (120) comprises voltage provisioning means (121) configured to supply a gate voltage to a gate terminal (102) of the first NMOS switch (100); current provisioning means (121) configured to provide a current; a first control stage (130) configured to provide and/or remove a connection between the gate terminal (102) of the first NMOS switch (100) and the voltage provisioning means (121), thereby switching the first NMOS switch (100) to an on-state and/or an off-state, respectively; and a first feedback control link (122, 140) between an output terminal (103) of the first NMOS switch (100) and the current provisioning means (121) configured to control the slew-rate of a voltage at the first output terminal (102).