HSIO Interconnection Fault Detection Using Segmented Switching
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Solution Overview
Problem
High-speed differential IO interconnections in electronic devices pose challenges in fault detection due to the potential masking of defects during testing, which can lead to system failures, and existing solutions like IEEE STD 1149.6 require significant engineering resources and extra hardware.
Innovation Solution
A fault analysis apparatus and method that utilize a test pattern source and switches to detect faults in interconnections between a transmitter and a receiver, leveraging existing on-chip functional and BIST circuitry to simplify the testing process without requiring additional analog circuitry or conformance verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If differential signaling is used in HSIO interconnections, then immunity against common noise is improved, but fault detection capability deteriorates due to potential masking of defects
Solution Approach 1:
The patent segments the testing process into multiple test configurations that selectively activate different signal paths. By dividing the differential pair testing into separate single-ended path tests, the method can isolate and detect faults that would otherwise be masked by the differential noise cancellation mechanism.
Solution Approach 2:
The patent introduces control switches as intermediary elements that can selectively connect or disconnect signal paths. These switches enable the test system to force single-ended signaling modes, acting as mediators that override the normal differential signaling behavior to expose latent faults.
2Difficulty of detecting and measuring
If IEEE STD 1149.6 is implemented for fault detection, then fault detection capability is improved, but device complexity and engineering resources increase significantly
Solution Approach 1:
The patent makes existing on-chip functional circuitry and BIST resources perform dual purposes: normal operational functionality and fault detection. By configuring existing switches and signal paths for testing purposes, the method eliminates the need for dedicated IEEE 1149.6 hardware while achieving comparable fault detection capabilities.
Solution Approach 2:
The patent enables the device to perform self-diagnosis using its own internal resources. The on-chip BIST circuitry and control switches are repurposed to automatically detect faults without requiring external testing equipment or additional dedicated test hardware, making the system self-sufficient for fault detection.
3Adaptability or versatility
If switches are used to configure test paths, then fault detection versatility is improved, but ease of operation deteriorates due to multiple test configurations
Solution Approach 1:
The patent employs dynamically controllable switches that can be programmed through control signals to establish different test configurations. This dynamic reconfigurability allows a single physical circuit to adapt to multiple testing scenarios, providing versatility without requiring separate dedicated circuits for each test type.
Data Source
AI summary
Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.