HSM Cryptographic Circuit Fault Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Hardware Security Modules (HSMs) lack functional safety features to prevent system failures that could lead to hazards, particularly in applications like the automotive field where ASIL-B compliance is required, and existing solutions for improving robustness against hardware random faults are either expensive or inefficient.
Innovation Solution
The solution involves reusing cryptographic processing circuit blocks for functional tests by implementing a second cryptographic processing unit that performs inverse operations and using a hash function accelerator to compare input and output data packets, allowing for robust detection of hardware faults without the need for dedicated redundant hardware, thereby enabling ASIL-B compliant functional safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HSM designs are used, then device complexity is low, but functional safety and robustness against hardware random faults are insufficient
Solution Approach 1:
The patent applies multi-functionality by making cryptographic processing circuit blocks serve dual purposes: performing cryptographic functions and performing functional safety tests. The same cryptographic processing units that handle encryption/decryption operations are reused to execute test sequences and generate comparison data packets, eliminating the need for separate dedicated test hardware and achieving functional safety without increasing hardware redundancy.
Solution Approach 2:
The patent uses copying by creating a second cryptographic processing unit that replicates the functionality of the first unit. This copied unit processes output data packets through inverse cryptographic operations to generate comparison data packets, which are then compared with input data packets to detect hardware faults. The copying approach enables fault detection without requiring extensive redundant hardware infrastructure.
2Reliability
If functional safety procedures are implemented, then robustness against hardware random faults improves, but computational effort and latency increase
Solution Approach 1:
The patent merges the functional safety verification process with the normal cryptographic processing workflow. By integrating the test mechanism into the existing processing path—where the second cryptographic processing unit operates on output data packets and compares results with input data packets—the system achieves fault coverage without requiring separate computational passes or additional latency-inducing steps.
3Reliability
If dedicated redundant hardware is used for functional safety, then detection of hardware faults improves, but hardware redundancy and device complexity increase
Solution Approach 1:
The patent eliminates dedicated redundant hardware by making existing cryptographic processing circuit blocks perform both cryptographic functions and functional safety tests. The same processing units that handle encryption/decryption are reused to execute test sequences, generating comparison data packets that enable fault detection without requiring separate redundant hardware components.
Solution Approach 2:
The system performs self-verification by using its own cryptographic processing capabilities to generate and compare data packets. The cryptographic processing circuits independently verify their own functionality by processing test data and comparing results, eliminating the need for external or dedicated redundant verification hardware.
Data Source
AI summary
An electronic device such as a hardware security module device comprises a first cryptographic processing circuit configured to receive input data packets and apply thereto a first cryptographic processing to provide output data packets. A second cryptographic processing circuit is provided in the device, configured to receive the output data packets, apply thereto a second cryptographic processing inverse to the first cryptographic processing, and provide comparison data packets as a result of applying the second cryptographic processing to the output data packets received. A comparison processing circuit in the device is configured to compare the input data packets with the comparison data packets, and to produce an error signal as a result of the input data packets being different from the comparison data packets.