HSS Clock-Gating Circuit for Synchronous Low-Power C2 Startup
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Solution Overview
Problem
High Speed Serializer-deserializer (HSS) cores face challenges in implementing power savings due to the need for precise clock signal gating, which requires fast current-mode logic (CML) latches that dissipate static power, especially at high frequencies like 11.25 GHz.
Innovation Solution
A power saving clock-gating method and circuit that includes a clock gate signal aligned through a series of latches, followed by a power down signal to turn off CML latches after C2 clocks are started, utilizing a CMOS power savings logic circuit to manage power in a phase locked loop (PLL) divider, converting CML signals to CMOS for efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current-mode logic (CML) latches are used to align clock gate signals at high frequency (11.25 GHz), then clock signal alignment precision is improved, but static power consumption increases
Solution Approach 1:
The patent implements periodic switching between CML latches (high-speed mode) and CMOS latches (low-power mode) based on operational requirements. The system alternates between using fast CML latches when clock alignment precision is critical and switching to power-efficient CMOS latches when high speed is not required, thereby achieving periodic action to balance performance and power consumption.
Solution Approach 2:
The patent changes the operational parameters of the latch circuit by switching between different latch types (CML and CMOS) with different characteristics. This parameter change allows the system to adapt between high-speed operation with precise clock alignment and low-power operation, directly resolving the contradiction between alignment precision and power consumption.
2Stability of the object's composition
If multiple CML latches are used in the clock-gating block to align clock signals, then clock synchronization across multiple HSS cores is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock-gating block into multiple independent latch units (both CML and CMOS types) that can be selectively activated. This segmentation allows the system to achieve clock synchronization across multiple HSS cores while managing complexity by only activating the necessary number of latches based on operational requirements, rather than permanently maintaining all latches in a complex configuration.
Solution Approach 2:
The patent designs the clock-gating block with universal latch units that can function in different modes (CML or CMOS) depending on requirements. This multi-functionality allows the same structural framework to achieve clock synchronization with varying degrees of complexity activated as needed, reducing the effective complexity while maintaining synchronization capability.
3Measurement precision
If C2 output divider is turned on synchronously for all PLLs, then phase locking precision is improved, but power consumption increases
Solution Approach 1:
The patent implements partial action by selectively activating only the necessary C2 output dividers and associated latches based on which HSS cores are currently active. Instead of turning on all dividers synchronously for all PLLs regardless of need, the system applies partial activation to achieve phase locking precision only where required, thereby reducing overall power consumption while maintaining precision for active cores.
Data Source
AI summary
A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the C2 clocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a C2 clock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the C2 clocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.