Hardware Transactional Memory Cache Balance

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Solution Overview

Problem

Hardware transactional memory (HTM) usage can lead to reduced cache availability for neighbor applications, causing performance degradation due to frequent cache flushes, which existing technologies fail to effectively manage.

Innovation Solution

A system and method that determine the HTM attrition rate using metrics like FLUSH_BY_HTM and CACHE_MISS, and regulate HTM transactions by limiting their size or preventing them from starting if the attrition rate exceeds a threshold, ensuring balanced cache usage and preventing performance degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If HTM transactions are allowed to proceed without regulation, then HTM atomicity and consistency are maintained, but cache availability for neighbor applications deteriorates due to frequent cache flushes

Engineering Contradiction:

ImproveHTM transaction atomicityVSAvoidcache availability

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The system implements feedback by monitoring the HTM attrition rate (ratio of cache flushes to cache misses) and using this information to dynamically regulate HTM transaction initiation. When the attrition rate exceeds a threshold, the system prevents new HTM transactions from starting, thereby feedback-controlled balancing between HTM reliability and cache availability for other applications.

Inventive Principle:

Principle #23Feedback

2Productivity

If HTM transactions are permitted to use cache freely, then HTM transaction performance is improved, but neighbor application performance deteriorates due to cache monopolization

Engineering Contradiction:

ImproveHTM transaction throughputVSAvoidcache monopolization

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system dynamically adjusts HTM transaction admission based on real-time cache conditions. The HTM attrition rate metric and threshold comparison enable dynamic regulation where HTM transactions are permitted when cache conditions are favorable and blocked when cache pressure is high, thus dynamically balancing HTM productivity with prevention of cache monopolization harmful effects.

Inventive Principle:

Principle #15Dynamics

3Quantity of substance

If the HTM attrition rate threshold is set low, then cache availability for neighbor applications is protected, but HTM transaction initiation is overly restricted

Engineering Contradiction:

Improvecache availability for non-HTM workloadsVSAvoidHTM transaction initiation rate

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The system uses parameter changes by adjusting the HTM attrition rate threshold to balance cache availability and HTM productivity. The threshold parameter serves as a control point where system administrators or the system itself can tune the aggressiveness of HTM regulation, allowing flexible adjustment between protecting cache availability for non-HTM workloads and maintaining HTM transaction initiation rates.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10754776B2Cache balance when using hardware transactional memory

Publication Date: 2020.08.25 KYNDRYL INC

AI summary

Systems and methods for cache balance when using hardware transactional memory are disclosed. A method includes: determining, by a computing device, a hardware transactional memory (HTM) attrition rate for a workload in a distributed computing environment; determining, by the computing device, whether or not the HTM attrition rate for the workload exceeds a predetermined threshold; and in response to determining that the HTM attrition rate for the workload does not exceed the predetermined threshold, the computing device causing a requested HTM transaction to begin.