Hardware Transactional Memory Split Database Transactions
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Solution Overview
Problem
In-memory databases face challenges in managing concurrent transactions across multiple threads due to cache line size restrictions and contention issues, leading to increased abort events and reduced performance.
Innovation Solution
The Split Transaction Execution (STE) method splits database transactions into Hardware Transactional Memory (HTM) transactions, employing optimistic concurrency control for reads and pessimistic control for writes, and uses local Last Committed version arrays to minimize contention and aborts, while maintaining compliance with cache line size restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If database transactions are executed concurrently across multiple threads, then database access performance is improved, but abort events increase due to contention and cache line size restrictions
Solution Approach 1:
The patent divides a database transaction into multiple HTM transactions, where each HTM transaction operates on a single cache line. This segmentation allows concurrent execution of multiple transactions without violating cache line restrictions, as each HTM transaction is isolated to its own cache line. The segmentation resolves the contradiction by enabling high concurrency (improving productivity) while preventing abort events caused by cache line conflicts (maintaining reliability).
Solution Approach 2:
The patent introduces HTM transactions as an intermediary mechanism between traditional database transactions and the underlying hardware cache system. The HTM transaction manager coordinates multiple HTM transactions to implement a complete database transaction, using read sets and write sets to track accessed cache lines. This intermediary layer enables concurrent execution while managing cache line restrictions, thus improving performance without increasing abort events.
2Reliability
If complex software mechanisms are used to manage transaction atomicity, then transaction reliability is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex software-based transaction management mechanisms with hardware-supported HTM transactions. The HTM functionality is implemented in the processor hardware, providing automatic atomicity guarantees for each HTM transaction. This substitution reduces software complexity while maintaining reliability, as the hardware automatically handles the atomicity requirements that would otherwise require complex software protocols.
Solution Approach 2:
Each HTM transaction is self-managing in terms of atomicity and isolation. The hardware automatically ensures that each HTM transaction executes atomically and isolates its operations to its designated cache line. This self-service approach eliminates the need for complex inter-transaction coordination software, reducing device complexity while maintaining transaction reliability.
3Quantity of substance
If HTM transactions exceed cache line size, then more data can be accessed per transaction, but abort events increase due to cache line restrictions
Solution Approach 1:
The patent segments the data access requirements of a database transaction into multiple HTM transactions, each confined to a single cache line. By dividing the overall data access workload across multiple cache line-sized HTM transactions, the system can access larger volumes of data (improving quantity of substance) while ensuring each individual HTM transaction remains within cache line size limits (maintaining reliability and preventing aborts).
Solution Approach 2:
The patent transitions from a single-dimension approach (one HTM transaction per database transaction) to a multi-dimensional approach (multiple HTM transactions per database transaction). By organizing HTM transactions along the dimension of cache line boundaries, the system can access more data overall while keeping each HTM transaction within size constraints, thus resolving the contradiction between data volume and success rate.
Data Source
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AI summary
A system for utilizing a Hardware Transactional Memory (HTM) for an in-memory database, comprising a processor adapted to execute a plurality of database transactions held concurrently to a shared in-memory database by splitting each of the plurality of database transactions to a plurality of HTM transactions, each of the plurality of HTM transactions is executed atomically to access one of a plurality of rows of a database, and for each of the plurality of HTM transactions perform the following operations - access a certain one of the plurality of rows, for a read HTM transaction, fetch content of a previous version of the certain row in case of a detection of another write HTM transaction concurrently writing the certain row, and for a write HTM transaction abort the write HTM transaction at initiation in case of the detection, and validate and commit the each HTM transaction through an additional HTM transaction.