Multi-Core HTML Injection Sampling Frequency Synchronization

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Solution Overview

Problem

Conventional techniques for HTML injection on multi-core intermediate devices result in inaccuracies due to unsynchronized core operations and lack of frequency specification for individual cores, leading to inconsistent data injection.

Innovation Solution

A method is introduced to establish a frequency of injection sampling across multiple cores by scaling the frequency based on the number of packet processing engines, with each core having a unique offset for data injection into responses, ensuring synchronized data injection across cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single frequency is specified for the intermediate device as a whole, then the device complexity is reduced, but the measurement precision of data injection frequency for individual cores deteriorates

Engineering Contradiction:
Improvefrequency specification complexityVSAvoiddata injection frequency accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the frequency specification from a device-level parameter to a core-level parameter. Each packet processing engine on each core is assigned its own frequency counter and injection frequency, allowing precise measurement and control of data injection frequency for individual cores while maintaining manageable complexity through localized frequency management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by allowing different frequency characteristics for different cores. Each core can have its own injection frequency and offset, enabling tailored frequency control for each packet processing engine based on its specific workload and performance requirements, rather than enforcing a uniform frequency across all cores.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If components on different cores work independently at runtime, then the ease of operation is improved, but the reliability of synchronized data injection deteriorates

Engineering Contradiction:
Improvecore operation independenceVSAvoiddata injection synchronization
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by establishing frequency relationships and offsets between cores during system initialization and configuration, before runtime operations begin. The master core's frequency is used to derive frequencies for slave cores in advance, and injection offsets are pre-calculated based on the number of packet processing engines, ensuring synchronized operation without requiring complex runtime coordination.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If frequency is scaled by the number of packet processing engines, then the productivity of data injection is improved, but the manufacturing precision of injection timing deteriorates

Engineering Contradiction:
Improvedata injection throughputVSAvoidinjection timing accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent uses parameter changes by dynamically adjusting the injection frequency based on the number of packet processing engines. The frequency is scaled proportionally to the number of PPEs, and corresponding offsets are calculated to maintain proper timing relationships. This allows the system to adapt frequency parameters to match the actual hardware configuration, optimizing both throughput and timing accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9497262B2Systems and methods for sampling management across multiple cores for HTML injection
Publication Date: 2016.11.15 CITRIX SYSTEMS INC
  • US9497262B2 patent drawing
  • US9497262B2 patent drawing
  • US9497262B2 patent drawing

AI summary

A method for sampling management includes establishing, for a multi-core intermediary comprising a plurality of packet evaluation components executing on a corresponding plurality of cores, a frequency at which the multi-core intermediary intercepts a response transmitted from a server to a client and injects data into the intercepted response. For each of the plurality of packet evaluation components, an offset and a frequency based on a number of packet evaluation components in the plurality of packet evaluation components is established, a combination of the established frequencies substantially similar to the frequency established for the multi-core intermediary. One of the plurality of cores intercepts a response from the server to the client, at a time specified by the frequency and the offset. The packet evaluation component executing on the one of the plurality of cores injects data into the intercepted response.