Hardware Thread Scheduler for ADAS Image Data Synchronization
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Solution Overview
Problem
Computer vision processing systems in advanced driver assistance systems (ADAS) face challenges in efficiently scheduling access to image data blocks for processing, particularly in generating image pyramids and managing bandwidth and data synchronization across multiple threads and hardware accelerators.
Innovation Solution
The implementation of a hardware accelerator thread scheduler (HTS) that uses pattern adaptors, transaction aggregators, and programmable delays to manage data synchronization, bandwidth control, and hang detection through watchdog timers, allowing for efficient data processing and synchronization across multiple threads and hardware accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple threads access image data blocks simultaneously for processing, then processing throughput is improved, but data synchronization complexity increases
Solution Approach 1:
The patent introduces a hardware accelerator thread scheduler as an intermediary component that mediates between multiple threads and image data blocks. The scheduler manages synchronization by coordinating access to shared data blocks, eliminating the need for complex software-based synchronization mechanisms while enabling parallel processing throughput.
Solution Approach 2:
The patent replaces software-based thread scheduling and synchronization mechanisms with a dedicated hardware accelerator. This hardware scheduler uses hardware-level atomic operations and memory ordering controls to manage data access between threads, substituting complex software coordination with simpler hardware-enforced synchronization.
2Speed
If hardware accelerators process image data in parallel, then processing speed is improved, but bandwidth management complexity increases
Solution Approach 1:
The hardware accelerator thread scheduler implements self-service bandwidth management by automatically detecting when data blocks are needed and coordinating access without external intervention. The scheduler monitors hardware accelerator status and autonomously manages data transfer timing, eliminating the need for complex external bandwidth control mechanisms.
Solution Approach 2:
The patent implements feedback mechanisms where the thread scheduler monitors the operational status of hardware accelerators and adjusts data access patterns accordingly. This feedback loop enables the scheduler to dynamically manage bandwidth allocation based on real-time hardware needs, optimizing processing speed while simplifying bandwidth management.
3Productivity
If image data is processed in blocks across multiple threads, then processing efficiency is improved, but data access synchronization becomes more complex
Solution Approach 1:
The patent segments image data into discrete data blocks that can be independently managed and accessed by different threads. The hardware accelerator thread scheduler then manages these segmented blocks through atomic operations, ensuring that each thread accesses only its assigned blocks or properly synchronized shared blocks, thereby maintaining reliability while improving processing efficiency.
Solution Approach 2:
The thread scheduler implements beforehand cushioning by pre-establishing synchronization protocols and memory ordering constraints before data access begins. The hardware-level atomic operations and memory barriers are set up in advance to prevent race conditions, ensuring reliable data access synchronization before parallel processing starts.
Data Source
AI summary
A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.