H-TSPC Prescaler Ring for Step-1 Millimeter-Wave Frequency Division
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Solution Overview
Problem
Existing frequency divider circuits face challenges in continuously varying the divide ratio, especially at millimeter wave frequencies, and achieving a divide ratio step size of one while maintaining high operating frequency and minimizing noise in wireless communication systems.
Innovation Solution
A hybrid true single-phase clock (H-TSPC) circuit architecture is employed, comprising non-ratio (NR) and ratio (R) logic circuits configured in a ring, allowing for continuous divide ratio adjustment with a step size of one, and incorporating a prescaler with DIV 1/2 and DIV 4/5 frequency dividers to optimize performance at millimeter wave frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider circuit is used to divide VCO output frequency at millimeter wave frequencies, then the frequency can be divided down for comparison with reference signal, but the ability to continuously change divide ratio with step size of one becomes challenging
Solution Approach 1:
The frequency divider is segmented into multiple stages: a first frequency divider stage that divides the VCO output by a first ratio, and a second frequency divider stage that divides by a second ratio. This segmentation allows the overall divide ratio to be continuously adjusted in steps of one while maintaining reliable operation at millimeter wave frequencies, as each stage operates at a manageable frequency level.
2Adaptability or versatility
If additional circuits are added to enable continuous divide ratio adjustment, then adaptability improves, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the divide ratio control functionality into the existing frequency divider structure itself, rather than adding separate control circuits. The first and second frequency dividers are integrated with control logic that jointly determines the overall divide ratio, allowing continuous adjustment without requiring additional multiplexers or complex external control mechanisms.
3Adaptability or versatility
If additional circuits are added to enable continuous divide ratio adjustment, then adaptability improves, but power consumption increases
Solution Approach 1:
The frequency divider circuit performs self-service by integrating the divide ratio control functionality within the divider structure itself. The control logic is embedded in the divider stages, allowing the circuit to adjust its own operation without requiring additional power-hungry control circuits or multiplexers, thereby achieving continuous divide ratio adjustment with minimal additional power consumption.
Data Source
AI summary
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.