Hub Chip Protection Circuit for Data Pin Backfeed Control
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Solution Overview
Problem
Hub chips experience operational issues due to interference from data pin voltages affecting power pins when external power is not provided, leading to abnormal operation or crashes upon power resumption.
Innovation Solution
A protection circuit with a voltage generation circuit, PMOS transistors, and detection circuits is implemented to adjust and regulate output voltages, and an electrostatic discharge circuit is included to prevent current interference, ensuring power pins remain at a low voltage during power interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the hub chip is coupled to external peripheral devices with downstream facing ports, then the number of connector ports is expanded and communication capability is improved, but voltage interference from data pins affects power pin stability causing abnormal operation or crashes
Solution Approach 1:
A protection circuit is introduced as an intermediary component between the data pins and power pins. This protection circuit includes voltage regulation modules that control the voltage levels on data pins and prevent them from interfering with the power pin voltage, thereby maintaining power stability while allowing the hub chip to support multiple connector ports
Solution Approach 2:
The voltage regulation function is segmented into separate protection circuits for different pin groups. Each protection circuit independently manages voltage levels for specific data pins and power pins, allowing the system to handle multiple connector ports while maintaining isolated voltage control for each pin group to prevent cross-interference
2Use of energy by moving object
If external power is not provided during power interruption, then power consumption is reduced, but data pin voltages enter power pin paths causing voltage to exceed 2.7V and trigger abnormal operation
Solution Approach 1:
The protection circuit performs preliminary voltage regulation on data pins before power interruption occurs. By pre-establishing voltage control mechanisms and clamping circuits, the system prevents data pin voltages from entering the power pin path during subsequent power interruptions, ensuring the power pin voltage remains below the 2.7V threshold even when external power is not provided
Solution Approach 2:
Before power interruption, the protection circuit activates voltage regulation modules to clamp data pin voltages to safe levels. This preliminary action ensures that when external power is removed and power consumption is reduced, the previously regulated voltage levels prevent any potential voltage interference from affecting the power pin stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection circuit effectively maintains power pins at a low voltage, preventing operational issues and ensuring the hub chip functions correctly upon power resumption, while also managing electrostatic discharge events.
Implementation Method 1
The PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage.
Implementation Method 2
The detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to a first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.
Implementation Method 3
The voltage generation circuit generates and adjusts an output voltage according to the voltage of the power pin and the voltage of the first data pin.
Implementation Method 4
The electrostatic discharge circuit is coupled between the first node and the first data pin. In response to an electrostatic discharge event occurring at the first data pin, the electrostatic discharge circuit provides a first discharge path to release an electrostatic discharge current from the first data pin, through the first node, to a ground node.
Implementation Method 5
The blocking element is coupled between the power pin and a first node to block current from entering the power pin from the first node.
Data Source
AI summary
A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.