Dynamic Huffman Table Generation With Reduced Latch Count
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Solution Overview
Problem
Existing compression accelerators face challenges in reducing the latch count required for symbol sorting during dynamic Huffman table generation, which is expensive in terms of area, power, and timing/wiring considerations.
Innovation Solution
The proposed solution involves mapping X-bit symbol frequencies from the LZ77 compressor to a Y-bit float-like representation, reducing the latch count by using a 10-bit value instead of a 24-bit counter, and dynamically adjusting the widths of the exponent and mantissa based on the LZ-count range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-precision symbol counts are used for sorting during dynamic Huffman table generation, then sorting accuracy is improved, but latch count and hardware area increase significantly
Solution Approach 1:
The patent changes the parameter representation from full-precision integer counts to a compressed format using exponent and mantissa fields. This parameter transformation allows the system to maintain sorting accuracy for frequency distribution while using fewer bits per symbol count, directly reducing the latch count from 6,864 to 2,860 latches for 286 symbols.
Solution Approach 2:
The patent segments each symbol count into two separate fields: an exponent field and a mantissa field. This segmentation allows independent optimization of each field's bit width based on the actual distribution of frequency values, enabling more efficient use of storage resources while preserving the relative ordering information needed for accurate sorting.
2Measurement precision
If full-precision symbol counts are used for sorting, then sorting accuracy is improved, but power consumption increases
Solution Approach 1:
By transforming the count parameter into exponent-mantissa representation, the patent reduces the total number of bits that need to be processed, stored, and compared during sorting operations. This parameter transformation directly reduces dynamic power consumption associated with latch switching and comparator operations while maintaining the precision needed for accurate frequency-based sorting.
3Measurement precision
If full-precision symbol counts are used for sorting, then sorting accuracy is improved, but timing and wiring complexity increase
Solution Approach 1:
The segmentation of count values into exponent and mantissa fields enables a more manageable sorting architecture. The exponent field can be used for coarse-grained sorting while the mantissa provides fine-grained differentiation, allowing the sorting network to be organized in stages with reduced wiring complexity at each stage compared to a monolithic full-precision sorting approach.
Data Source
Figure 1A~1B
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AI summary
Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.