Huge Page Cache Address Mapping for Color Bit Partitioning
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Solution Overview
Problem
The existing technologies face challenges in using both huge page technology and page-coloring based Cache partition simultaneously due to a contradiction where the page table's physical page number does not overlap with the cache set index, preventing effective cache partitioning and leading to increased TLB and LLC contention, especially in multi-core architectures.
Innovation Solution
The proposed solution involves mapping some bits of the physical page number of a huge page to a cache set index, allowing the operating system to control and color these bits, thereby enabling simultaneous use of huge page technology and page-coloring based Cache partition, by restructuring the address mapping to include a cache set index formed by high-order and low-order bits, and optionally exchanging address parts to create a pseudo page address for effective cache access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If huge page technology is used to reduce TLB contention, then TLB miss rate is reduced, but the physical page number no longer overlaps with cache set index, preventing cache partitioning
Solution Approach 1:
The patent segments the physical page number into multiple parts, specifically extracting certain bits from the physical page number to form a color bit that is then mapped to the cache set index. This segmentation allows the system to simultaneously maintain huge page benefits for TLB performance while enabling cache partitioning through the extracted color bits.
Solution Approach 2:
The patent introduces a new dimension by creating a color bit field that bridges the physical page number and cache set index. Instead of directly using the physical page number for cache indexing, the system projects specific bits to a new color bit dimension, which then maps to cache sets, enabling cache partitioning without affecting the huge page structure.
2Reliability
If page-coloring based Cache partition is implemented, then cache contention between cores is reduced, but it cannot be used simultaneously with huge page technology due to address mapping conflicts
Solution Approach 1:
The patent segments the address mapping process into multiple stages: first mapping virtual addresses to physical addresses using huge pages, then extracting specific bits from the physical page number to form color bits, and finally mapping these color bits to cache sets. This multi-stage segmentation allows both huge page technology and page-coloring cache partition to coexist.
Solution Approach 2:
The patent introduces color bits as an intermediary element between the physical page number and the cache set index. These color bits serve as a mediator that enables cache partitioning without interfering with the huge page address mapping, allowing both technologies to work together harmoniously.
3Device complexity
If traditional address mapping is used, then hardware complexity is low, but TLB and cache contention increases with multiple cores and large data sets
Solution Approach 1:
The patent performs preliminary action by pre-defining the mapping relationship between physical page number bits and cache set index bits through the color bit mechanism. This pre-established mapping relationship allows the system to automatically handle cache partitioning without adding complex real-time decision-making hardware, thus maintaining low hardware complexity while improving performance under contention.
Data Source
AI summary
A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.