High Voltage IC Capacitor Mesa Structure

The patent transitions from planar capacitor structures to three-dimensional stacked capacitor structures. Multiple capacitor units are stacked vertically on the same silicon substrate, utilizing the vertical dimension to increase capacitance without expanding the silicon footprint. This stacking approach allows achieving high breakdown voltages through proper dielectric layer design while maintaining compatibility with standard semiconductor processing, thus avoiding wafer warpage issues associated with excessively thick single-layer dielectrics.

The capacitor structure is divided into multiple discrete capacitor units stacked vertically. Each capacitor unit consists of its own dielectric layer and electrode structures. This segmentation allows each layer to be optimized independently for breakdown voltage requirements, while the overall stacked structure achieves the desired total capacitance. The modular approach also simplifies manufacturing by using repeated deposition and patterning cycles rather than requiring a single excessively thick dielectric layer.

The invention moves the scaling direction from lateral (planar) expansion to vertical stacking. Instead of increasing dielectric layer thickness to achieve higher capacitance and voltage ratings, the patent stacks multiple capacitor units vertically on the same silicon footprint. This approach dramatically reduces silicon area consumption while maintaining or enhancing breakdown voltage capability through proper dielectric design in each stacked unit.

Multiple capacitor units are nested vertically within the same planar footprint on the silicon substrate. Each capacitor unit contains dielectric and electrode structures that are stacked one above another, similar to nested dolls. This nesting approach maximizes the use of vertical space, allowing high capacitance and high breakdown voltage to be achieved without increasing the silicon area occupied by the capacitor.

The thick dielectric requirement is segmented into multiple thinner dielectric layers deposited in sequential steps. Each layer can be deposited using standard semiconductor CVD or PECVD processes at controlled thicknesses. This segmentation allows the use of conventional deposition equipment and process parameters, avoiding the need for single-step ultra-thick deposition that would require specialized equipment and longer processing times, thereby maintaining manufacturing efficiency.

The capacitor structure is built through periodic repetition of deposition and patterning cycles. Each cycle deposits a dielectric layer and forms associated electrode structures. This periodic manufacturing approach using standard process cycles improves manufacturing efficiency compared to forming a single thick dielectric layer, as it allows for better process control, shorter individual deposition times, and utilization of existing semiconductor manufacturing equipment and methodologies.