HV-CMOS Sensor Backside Biasing for Radiation Tolerance
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Solution Overview
Problem
HV-CMOS sensors face challenges in maintaining irradiation tolerance, longevity, and sensitivity, especially under high radiation conditions such as those expected in future particle physics experiments like the HL-LHC and FCC-hh.
Innovation Solution
The proposed HV-CMOS sensor design features a p-substrate with pixel structures on the topside and an HV bias contact electrically coupled only to the doped p+ layer on the backside, allowing for increased pixel density and resolution while maximizing the through-thickness spacing between HV bias contacts and pixel structures, thus enhancing irradiation tolerance and longevity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If HV bias contacts are placed on the topside near pixel structures, then ease of operation is improved, but irradiation tolerance deteriorates due to reduced through-thickness spacing
Solution Approach 1:
The patent moves HV bias contacts from the topside (2D plane) to the backside of the substrate, utilizing the third dimension (through-thickness direction) to resolve the contradiction. This spatial relocation increases the through-thickness spacing between HV bias contacts and pixel structures, thereby improving irradiation tolerance while maintaining operational accessibility through backside contact routing
2Measurement precision
If pixel density is increased to improve resolution, then measurement precision is improved, but device complexity increases due to reduced spacing between pixel structures
Solution Approach 1:
The patent resolves the spacing constraint by utilizing the through-thickness dimension. HV bias contacts are positioned on the backside at maximum distance from pixel structures, allowing increased pixel density on the topside without compromising electrical isolation. This dimensional separation enables finer pixel pitch while maintaining adequate spacing for manufacturability and reliability
3Reliability
If through-thickness spacing between HV bias contacts and pixel structures is increased, then irradiation tolerance is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent achieves increased through-thickness spacing by positioning HV bias contacts on the backside, which actually simplifies manufacturing. The backside contact approach allows standard front-side fabrication processes to complete pixel structures first, followed by separate backside processing for HV contacts. This separation of operations reduces process complexity compared to integrating HV contacts on the topside with pixel structures
Solution Approach 2:
The patent introduces the substrate backside as an intermediary location for HV bias contacts. This intermediary positioning enables electrical connection to pixel structures through the substrate thickness, achieving the desired spacing while maintaining manufacturability through established semiconductor fabrication techniques for backside contact formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved irradiation tolerance and longevity by allowing higher HV bias voltages before breakdown, maintaining signal quality and detection efficiency even after extended exposure to high radiation levels.
Implementation Method 1
HV-CMOS devices may be biased to high voltages for fast charge collection by drift
Implementation Method 2
fast charge collection by drift
Implementation Method 3
If a particle carries an electric charge, it will leave a trace in each layer of silicon
Implementation Method 4
the sensing cell or pixel generates a small electric signal when a charged particle traverses it
Data Source
AI summary
A High Voltage Complementary Metal-Oxide-Semiconductor, HV-CMOS, sensor comprising a p-substrate having a topside and a backside;wherein the topside comprises:an array of mutually spaced apart pixel structures, including a first pixel structure, therein and/or thereon, wherein the first pixel structure comprises: a set of PMOS and NMOS transistors, including a first PMOS transistor having an n-well, SN, layer, and a first NMOS transistor having a p-well, SP, layer; a deep n-well, DN, structure having a DN layer; a p-type buried, BP, layer disposed to mutually isolate the SN layer and the DN layer; an n-type buried, BN, layer providing a SN/BN/DN stack; and a set of contacts, including a first contact, electrically coupled to the DN layer via the SN/BN/DN stack;wherein the backside comprises:a doped p+ layer therein and/or thereon; andwherein the sensor comprises an HV bias contact electrically coupled only to the p+ layer, for backside biasing thereof.