High Voltage Control Circuit for Non-Volatile Memory Safe Operating Area

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Solution Overview

Problem

In non-volatile memory devices using common source line (CSL) architecture, controlling high voltage signals to maintain the safe operating area (SOA) of transistors is challenging, as high voltage signals can cause transistor damage if not properly managed.

Innovation Solution

A high voltage control circuit is implemented to manage both high voltage (HV) and low voltage (LV) signals for operations like programming, erasing, and reading, ensuring that transistors in non-volatile memory cells remain within their safe operating area by applying appropriate voltage biases through a common source line shared among multiple cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If high voltage signals are applied to program non-volatile memory cells, then programming capability is achieved, but transistor damage risk increases

Engineering Contradiction:

Improveprogramming capabilityVSAvoidtransistor safety

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

A dedicated high voltage control circuit is introduced as an intermediary between the voltage source and the memory cells. This control circuit generates and regulates the high voltage signals, ensuring they remain within safe operating limits while still achieving effective programming of the charge trapping layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The control circuit dynamically adjusts voltage parameters (magnitude, duration, timing) based on the specific programming requirements and transistor safety constraints. By precisely controlling these electrical parameters, the system achieves reliable programming without exceeding transistor breakdown thresholds.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If common source line architecture is used to reduce silicon area, then area efficiency improves, but control of high voltage signals becomes more difficult

Engineering Contradiction:

Improvesilicon areaVSAvoidhigh voltage signal control

Core Design Contradiction:

Area of moving objectVSDevice complexity

Solution Approach 1:

The high voltage control circuit is designed to serve multiple memory cells simultaneously through the shared common source line. A single control circuit manages high voltage distribution across numerous cells, performing multiple functions (voltage generation, regulation, timing control) that would otherwise require separate circuits for each cell.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control circuit incorporates feedback mechanisms to monitor the state of memory cells and adjust high voltage signals accordingly. This ensures that cells are programmed only when ready and prevents over-voltage conditions that could damage transistors in the shared architecture.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10373688B2High voltage architecture for non-volatile memory

Publication Date: 2019.08.06 LONGITUDE FLASH MEMORY SOLUTIONS LTD

AI summary

A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).