HV ESD Bipolar Transistor Integration in Vertical FET Technology

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Solution Overview

Problem

FinFETs in smaller technology sizes are susceptible to electrostatic discharge (ESD) failures due to increased current density, and existing ESD protection methods are limited by on-chip area constraints, especially for high voltage devices which are difficult to build on finFET or vertical field-effect transistor (VFET) technology.

Innovation Solution

Integration of high voltage (HV) ESD PNP/NPN bipolar transistors in a VFET process, involving the formation of n-doped and p-type well regions, high voltage double diffusion drain regions, and fin structures with gate all around (GAA) configurations, along with epitaxial source/drain and contact structures, to enhance ESD protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If finFETs are used in smaller technology sizes, then drive current and short-channel effect prevention are improved, but susceptibility to ESD failure increases due to increased current density

Engineering Contradiction:

Improvedrive currentVSAvoidESD failure susceptibility

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The patent combines the VFET structure with bipolar transistor elements to form a merged device that integrates the high drive current capability of the VFET with the ESD protection capabilities of the bipolar transistor, allowing the same structure to provide both functions simultaneously

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The device is segmented into distinct functional regions including the VFET active area, bipolar base region, and collector region, allowing each segment to optimize its specific function while working together as an integrated structure

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If on-chip area is reduced to meet scaling demands, then device integration is improved, but ESD protection capability deteriorates due to limited current shunting capabilities

Engineering Contradiction:

Improveon-chip areaVSAvoidESD protection capability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar ESD protection structures to a vertical three-dimensional structure utilizing the depth dimension with stacked regions (VFET channel, bipolar base, and collector), enabling effective ESD protection within a minimal footprint by exploiting the vertical space above the substrate

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bipolar transistor structure is nested within the VFET structure, with the bipolar base and collector regions positioned beneath or adjacent to the VFET active area, allowing the ESD protection function to be embedded within the same device footprint

Inventive Principle:

Principle #7Nested doll (Nesting)

3Length of moving object

If channel width is reduced in smaller technology nodes, then scaling is achieved, but current density during ESD events increases leading to gate oxide breakdown

Engineering Contradiction:

Improvechannel widthVSAvoidgate oxide breakdown risk

Core Design Contradiction:

Length of moving objectVSManufacturing precision

Solution Approach 1:

The bipolar base region acts as an intermediary between the VFET active area and the collector, providing a low-impedance current path that mediates the ESD current flow and prevents it from concentrating through the narrow VFET channel, thereby protecting the gate oxide from breakdown

Inventive Principle:

Principle #24Intermediary (Mediator)

4Adaptability or versatility

If high voltage devices are designed on finFET or VFET technology, then device integration is improved, but difficulty in building HV devices increases

Engineering Contradiction:

Improvedevice integrationVSAvoidHV device fabrication difficulty

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent creates a universal device structure that can operate in multiple voltage regimes and modes, combining the VFET for normal operation with the bipolar transistor for high voltage ESD protection, allowing the same fabrication process to produce both low-voltage and high-voltage capable devices

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10290626B1High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET) technology and method for producing the same

Publication Date: 2019.05.14 GLOBALFOUNDRIES US INC

AI summary

Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.