HV-ESD Field Plate Structure for Low Parasitic Capacitance

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Solution Overview

Problem

Conventional ESD devices for high-frequency circuit applications, such as ASIC high-speed serial links and power amplifiers, suffer from high parasitic capacitance that affects normal circuit operation when the ESD is off.

Innovation Solution

A high-voltage electrostatic discharge (HV-ESD) device with a polysilicon field plate on a thermally grown oxide (LOCOS) structure, which includes a uniform thickness and partial overlap with the base region, reducing turn-on resistance and enhancing ESD performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD devices (e.g., ESD diodes) are used for protection, then ESD protection function is achieved, but parasitic capacitance increases which impacts normal circuit operation

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The ESD protection function is segmented into multiple parallel paths: a low-capacitance path for normal operation and a high-current path for ESD events. The HBT device structure separates the protection function from the signal path, allowing the ESD device to activate only during surge events while maintaining low parasitic capacitance during normal operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the operational parameters of the ESD device by utilizing a HBT structure with controlled doping profiles and junction depths. By optimizing the base region doping concentration and width, the device achieves low parasitic capacitance in the off-state while maintaining high breakdown voltage and adequate ESD protection capability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ESD protection devices are added to protect IC devices, then reliability against ESD events is improved, but device complexity increases

Engineering Contradiction:
ImproveESD protectionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The HBT-based ESD device serves multiple functions within a single structure: it provides ESD protection, maintains low parasitic capacitance for high-frequency operation, and integrates seamlessly with standard CMOS or BiCMOS processes. The same device structure that protects against ESD also functions as part of the normal circuit operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The ESD device automatically activates during ESD events without requiring external control circuitry. The inherent breakdown characteristics of the HBT structure cause it to conduct during voltage surges, providing self-protecting functionality that simplifies the overall circuit design.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The HV-ESD device exhibits stable DC leakage current and increased ESD performance by up to 35% compared to conventional PNP or diode structures, addressing the high parasitic capacitance issue.

Implementation Method 1

a thermally grown insulator region on the semiconductor material extending from the base region to the collector region

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS20250331271A1High-voltage electrostatic discharge device
Publication Date: 2025.10.23 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US20250331271A1 patent drawing
  • US20250331271A1 patent drawing
  • US20250331271A1 patent drawing

AI summary

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge devices and methods of manufacture. The structure includes: a semiconductor material including an emitter region, a base region adjacent to the emitter region; and a collector region; a thermally grown insulator region on the semiconductor material extending from the base region to the collector region; and a field plate on the thermally grown insulator region and overlapping with the base region.