HV FET Gate Spacer Layout to Reduce Electron Trapping
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Solution Overview
Problem
High voltage field effect transistors suffer from surface breakdown voltage and reliability issues due to electron trapping in silicon nitride gate sidewall spacers, which are exacerbated by additional dielectric layers used in metal silicide formation.
Innovation Solution
Implementing different gate sidewall spacer configurations for p-type and n-type high voltage transistors, with elongated silicon nitride spacers acting as partial silicide blockers and ion implantation masks in n-type transistors, and narrower silicon nitride spacers in p-type transistors, to improve reliability and reduce electron trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extended low doped drain is used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the extended low doped drain structure from the transistor design. Instead of using the complex extended LDD approach, the invention uses a simpler gate spacer configuration that achieves the same surface breakdown protection without the additional process steps and structural complexity associated with extended LDD regions.
Solution Approach 2:
The patent inverts the traditional approach by placing the protective function directly on the gate spacer structure rather than using a separate extended LDD region. The gate spacer is configured to extend over the active region and provide surface breakdown protection, reversing the conventional role assignment where LDD structures provided this protection.
2Ease of manufacture
If silicon nitride gate sidewall spacers are used for metal silicide formation, then silicide formation is enabled, but electron trapping increases and reliability decreases
Solution Approach 1:
The patent applies local quality by using different dielectric materials in different regions of the gate spacer structure. Specifically, silicon oxide is used in portions of the gate spacer where it will contact or be near the active region, while silicon nitride is used in other portions. This localized material selection allows silicide formation capabilities where needed while minimizing electron trapping in regions closest to the active region.
Solution Approach 2:
The gate spacer is segmented into multiple portions with different dielectric materials. The structure is divided such that different materials are placed in different spatial zones, allowing each segment to perform its specific function - silicon nitride for silicide formation support and silicon oxide for reducing electron trapping near the active region.
3Ease of manufacture
If additional dielectric layers are added for metal silicide formation, then silicide formation is achieved, but electron trapping is exacerbated and leakage current increases
Solution Approach 1:
The patent uses local quality by strategically placing silicon oxide dielectric material in the gate spacer portions that are closest to or in contact with the active region. This localized use of low-trapping material reduces the harmful electron trapping effect and associated leakage current, while still maintaining the necessary dielectric structure for metal silicide formation in other areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of high voltage transistors by minimizing electron trapping and reducing leakage currents, thereby improving the performance and longevity of the devices.
Implementation Method 1
elongated silicon nitride spacers acting as partial silicide blockers and ion implantation masks in n-type transistors
Data Source
AI summary
A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.